Mti Technology Corporation

Robert Craig Bagley

A memory system including a main memory such as a cache memory and a shadow or back-up cache memory in conjunction with a write cache is disclosed. The shadow memory is coupled to the same data bus as the main memory and is written to simultaneously. Thus, there is no latency between writing to the main memory and writing to the shadow memory. Redundancy is provided for by having a switching circuit which allows control of the shadow memory to be transferred to a second controller upon failure of a first controller. A unique layout arrangement for a RAID (redundant array of independent disks) chassis is also described in which back-to-back circuit boards are mounted in the center of the chassis and a main bus on one board becomes the shadow bus on the other board, providing a mirror arrangement for the circuit boards.

Cache ram using a secondary controller and switching circuit and

A clock failure detection circuit which monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of them can clock a logic circuit to determine if the clock is at the proper level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, a bad output signal will be provided whenever the clock is high instead. This could be caused by the clock being stuck high, or by an irregular pulse width.

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San Jose, CA, United States of America

Robert Craig Bagley