Sun Microsystems, Inc.

Robert Cmelik

Edmund Joseph Kelly

Shing I Kong

Michael L Powell

David Ditzel

A backward compatible addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers. The computer system of the present invention has a processor capable of manipulating numbers having precision S, where S is a power of 2. The memory locations are specified in an instruction address field by an n-bit logical address ##EQU1## Each S-precision number is stored in a group of S memory locations accessed by an m-bit physical address ##EQU2## Each memory location is capable of storing a single precision number. Addressing logic for addressing the memory locations with the logical addresses includes alignment logic for setting:

Memory addressing scheme for increasing the number of memory locations

The present invention enables a computer system to store from register files to memory, and restore from memory back to the register files, data from programs designed to operate in accordance with a first word size, as well as programs designed to operate in accordance with a second word size. This is accomplished without an increase in hardware and without requiring modification of existing software. In particular, an indication is utilized at the procedure level to designate whether a particular procedure is using words of a first or second word size. Preferably, this indication is placed in a first predetermined bit position in the stack pointer of the procedure. When a save occurs, certain contents from the register file are saved to memory along with the stack pointer. Under certain circumstances, the word size indication is moved to a second predetermined bit position within the stack pointer which is stored in a predesignated stack pointer address in the save area. When the contents are restored from memory, back to the register file, the indication is reviewed in the stack pointer address and serves to determine the word size of the procedure being restored.

Extending computer architecture from 32-bits to 64-bits by using the

A method and apparatus are provided for enabling a computer that is capable of running programs utilizing different address sizes to run those programs without having to modify the computer's hardware. A mask register is used to identify bits of a sum of register addresses that are valid for the program that is running. The number of valid bits in the register mask can be changed to correspond to the addressable memory size for different programs.

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Sunnyvale, CA, United States of America

Robert Cmelik