Texas Instruments Corporation

Robert Christopher Baumann

John Anthony Rodriguez

Richard Allen Bailey

John Michael Carulli, Jr

Timothy Z Hossain

Xiaowei Zhu

In some examples, a system comprises a nuclear event detector (NED) to issue a nuclear event status signal, a primary power supply to issue a power status signal, a backup power supply, a non-volatile storage, and a processor coupled to the non-volatile storage and the NED and switchably coupled to the primary and backup power supplies. The processor is to store a state of the processor to the non-volatile storage based on the nuclear event status signal, and the processor is to selectively receive power from either the primary power supply or the backup power supply based on the nuclear event status signal and the power status signal.

Storing processor states during nuclear events

A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

Method and circuit enabling ferroelectric memory to be fixed to a stable state

Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all 1's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

Random number generation in ferroelectric random access memory (FRAM)

Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all l's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

Integrated circuits and methods for deactivating user circuit operation with one or more wide channel sensing transistors biased to an on condition for exposure to total ionizing dose and then to an off condition for measurement and comparison of a leakage current or threshold voltage parameter to a predetermined reference, and a deactivation circuit selectively disables operation of the user circuit if the sensed parameter is greater than or equal to the reference.

Integrated circuit with automatic total ionizing dose (TID) exposure deactivation

Integrated circuits as well as fabrication and operating methods are presented in which user circuitry of the IC is selectively disabled in response to detection of a single event latchup condition in a sensing circuit that is prone to latchup in response to ionic radiation at a specific linear energy transfer level.

Integrated circuit with automatic deactivation upon exceeding a specific ion linear energy transfer (LET) value

A method includes testing to failure a plurality of semiconductor test structures, measuring a parameter of each semiconductor test structure after experiencing a failure, and generating a cumulative probability distribution function (CPDF) of cumulative probability versus the measured parameter after failure for the plurality of semiconductor test structures. The method further includes performing simulations for a circuit having an area using a model of a transistor that mimics the failure to determine a parameter threshold value that defines a minimum acceptable performance level of the circuit, determining a cumulative probability value from the CPDF that a transistor will not have the parameter at a level below the parameter threshold value, adjusting a value of the area of the circuit based on the cumulative probability value, and computing a first reliability value based on the adjusted area value.

Reliability determination taking into account effect of component failures on circuit operation

The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

Method of fabricating an integrated circuit to improve soft error performance

The present invention pertains to radiation sources that mimic radiation environment(s) encountered by packaged semiconductor devices. The sources are suitable for use in test systems operative to test for soft error and/or failure rates in devices sensitive to such radiation. The radiation is highly active to exacerbate soft error rates and thereby accelerate testing and reduce test times. The sources are also relatively uniformly distributed within a medium to simulate the direction(s) and energy spectra of radiation that would actually be encountered by semiconductor devices in device operation.

High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments

Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.

Growing community of inventors

Dallas, TX, United States of America

Robert Christopher Baumann