Chartered Semiconductor Manufacturing Ltd (Corporation)

Robert Chin Fu Tsai

Yung-Tao Lin

Sik On Kong

Paul Proctor

Seng-Keong Victor Lim

Dai Feng

A polish apparatus for planarizing wafers and films over wafers comprising the following. A substrate chuck for holding a substrate with a surface to be polished thereof being directed about vertically. A first drive means for rotating the substrate chuck. A polishing head having a polishing surface which is adjacent to the substrate during the polishing of the substrate. The polishing surface of the polishing head is smaller than the surface of the substrate. A polishing solution supply means for supplying a polishing solution through the polishing head to the substrate held by the substrate chuck. A reciprocating means for reciprocally moving the polishing head on the surface to be polished. A pressing means for pressing the polishing pad against a substrate held by the substrate chuck by way of the polishing head. The polish head is preferably comprised of one piece of molded polymer. No polish pad is used.

Chemical-mechanical polisher hardware design

A method of fabricating an LCD-on-silicon device, comprising the following steps. A semiconductor structure having a control transistor formed therein is provided. The control transistor having a source and a drain. An interlevel dielectric (ILD) layer over the semiconductor structure is provided. Source/drain (S/D) plugs contacting the source and drain through contact openings in said ILD layer are provided. M1 lines are formed over the ILD layer and connected to at least the S/D plugs. An M1 intermetal dielectric (IMD) layer is deposited and patterned over the M1 lines to form M1 contact openings exposing at least some of the M1 metal lines. M1 metal plugs are formed within the M1 contact openings and M2 metal islands connected to, and integral with, at least the M1 metal plugs. The M2 metal islands having exposed side walls. Sidewall spacers are formed on the exposed M2 metal islands side walls. A second M2 metallization layer is deposited and patterned over the M2 metal islands to form a shielding layer adjacent to and contiguous with the sidewall spacers. The M2 metal islands, sidewall spacers, and shielding layer form a light shielding layer. At least one additional dielectric and conductive layer is formed over the light shielding layer and the M1 intermetal dielectric (IMD) layer. LCD pixels are then formed thereover.

Growing community of inventors

Singapore, Singapore

Robert Chin Fu Tsai