Intel Corporation

Amazon Technologies, Inc.

Robert Charles Swanson

Vincent J Zimmer

Mallik Bulusu

Michael A Rothman

Palsamy Sakthikumar

Robert Bruce Bahnsen

Robert W Cone

Mahesh S Natu

Piotr Michael Kwidzinski

Mohan J Kumar

Madhusudhan Rangarajan

Janusz Jurski

Robert S Gittins

Theodros Yigzaw

Mariusz Oriol

Babak B Nikjou

Sarathy Jayakumar

Narayan Ranganathan

Rajesh S Parthasarathy

Malay Trivedi

Frank Binns

Baskaran Ganesan

Thanunathan Rangarajan

Eswaramoorthi Nallusamy

Anil S Keshavamurthy

Gautam Doshi

Pawel Szymanski

Larry D Aaron, Jr

Mariusz Stepka

Piotr Sawicki

John R Lindsley

William J O'Sullivan

Rajesh Nagaraja Murthy

Murugasamy K Nachimuthu

Rahul Khanna

Ashok Raj

Daniel Nemiroff

John V Lovelace

Shamanna M Datta

Christopher James BeSerra

Nathan Pritchard

Troy Lawson Bevis

Sugumar Govindarajan

Rajesh Poornachandran

Darin Lee Frink

Mark A Schmisseur

Anthony Nicholas Liguori

Raghunandan Makaram

Stephen S Pawlowski

Eugene Gorbatov

Herbert H Hum

Mingqiu Sun

Jiewen Yao

John S Howard

Kirk D Brannock

Karunakara Kotary

Ramamurthy Krithivas

Nimrod Diamant

Anil K Kumar

Dimitrios Ziakas

Thomas M Slaight

James Steven Burns

Gopinatth Selvaraje

Michael Kinney

Giri P Mudusuru

Michael Jon Moen

Filippo Sironi

Eric R Wehage

Ganesh Kumar

David N Lombard

Asher M Altman

Russell J Wunderlich

David Bubien

C Brendan Traw

Kanivenahalli Govindaraju

Matthew E Tolentino

Ronald N Story

Tsung Ho Wu

Greg P McGrath

William R Hannon

Miles F Schwartz

Celeste M Brown

Isaac W Oram

Fernando A Lopez

Ravi Akundi Murty

Pankaj Kumar Rai

David P Larsen

Tony S Baker

Chris Ackles

Waldemar Piotrewicz

Millik Bulusu

Shammanna M Datta

Mallik Bulusa

Tinghui Wang

Nandagopal Sathyanarayanan

Maulik Kapuria

Yuhui Zheng

Sang Phill Park

Kasper Wszolek

A host server computer with an uncorrectable memory error can be repaired without a reboot operation. While initially booting a hypervisor, a special software Application Programming Interface (API) can be loaded between a BIOS System Management Mode (SMM) code and the hypervisor. Once the host server computer is booted and a number of virtual machines are executing, a memory error (e.g., uncorrectable error correction code (UECC)) can occur. In response, the hypervisor calls into the special software API identifying the defective memory rows that the BIOS needs to repair. The BIOS starts a soft Post Package Repair (PPR) process on those rows and gives back control to the hypervisor. When the repair is completed, the hypervisor loads a scrubbing virtual machine and validates that the memory is corrected. After the repair is validated, the hypervisor allows the available partition to take a new customer instance.

Runtime memory repair without requiring a reboot of a server computer

An interposer card and a virtualization offloading card are provided for installation in a third-party server to integrate the third-party server into a cloud service provider network. The interposer card includes a baseboard management controller that interfaces with a management console of the cloud service provider network. This allows the third-party server to be converted into a server controlled by the cloud service provider network. Additionally, the baseboard management controller of the interposer card acts as a firewall between the third-party server and a management control network of the cloud service provider network. The interposer card and the virtualization offloading card are installed in a chassis of the third-party server via an expansion slot without requiring modification of the hardware or firmware of the third-party server.

Hardware for integration of servers into a management network

Approaches in accordance with various embodiments provide for the management of system event data in a computing device. In particular, various embodiments provide an intelligent persistent buffer for system event log (SEL) messages. A SEL message can be generated by system BIOS on a computing device, which can send this message over an appropriate interface to a target recipient, such as the BMC. Instead of being received directly to the BMC, however, the SEL message can be received to a logic device, such as a CPLD, that is able to analyze the message, determine that the message relates to an important system event, and can cause this message to be stored to a persistent buffer. The BMC can then subsequently request the buffered SEL message from the logic device to take an appropriate action.

Event communication management

When a computer boots up, a Basic Input/Output System (BIOS) configures system memory to have a crash memory area within the system address map, which can be used by a processor to dump crash memory data. When an error event occurs, the processor can initiate a dump to the crash memory area. Any desired data can be placed into the crash memory area, but typical data can include a state of registers in the processor. The processor then sets a flag, such as an external pin, indicating that the crash memory data is ready to be read. The flag can be read by a secure processor, which then reads the crash memory area at normal memory access speeds using the system bus. For example, the secure processor can access the crash memory area using Direct Memory Access (DMA) reads over a PCIe system bus.

Obtaining computer crash analysis data

Various systems and methods for obtaining vendor information using mobile internet devices are described herein. An inquiry for a product or service is received from a user. A location for the receipt of the product or service is received. Vendor information of a vendor of the product or service proximate to the location is determined, with the vendor information including a price for the product or service, and a wait time to receive the product or service. The vendor information is then transmitted to the user.

Obtaining vendor information using mobile internet devices

Systems and methods for an integrated reliability, availability, and serviceability (RAS) state machine are provided. Handling of RAS events by the Basic Input Output System (BIOS) of an integrated circuit device can result in lost processing time on the processing cores of a multi-core processor resulting from numerous system management interrupts generated by the BIOS. To reduce lost processing time, a dedicated state machine can execute instructions to handle RAS events independently of the BIOS and minimize the number of system management interrupts.

Integrated reliability, availability, and serviceability state machine for central processing units

Embodiments of the claimed invention include a computing device having a host processor for executing a firmware environment and a manageability controller. The firmware environment reserves a frame buffer in main memory and loads a graphics protocol driver to provide the frame buffer to an operating system of the computing device. The operating system renders graphical images to the frame buffer using a graphics driver. The manageability controller reads the graphical image from the frame buffer and may transmit the graphical image to a remote computing device. In response to a fatal error of the computing device, the manageability controller may store the graphical image to a non-volatile storage device. The host processor may assert a host reset signal in response to the fatal error, and the manageability controller may send an acknowledgment to the host processor after storing the graphical image. Other embodiments are described and claimed.

Technologies for headless server manageability and autonomous logging

Systems, apparatuses and methods may provide for technology that detects an initiation of a reset flow in a network edge computing system and determines one or more attributes of one or more long flow instructions during the reset flow, wherein the one or more attributes include a latency of the one or more long flow instructions. Additionally, the one or more attributes may be documented via an interface that is accessible by one or more of an operating system or a hypervisor associated with the network edge computing system.

Operating system visibility into system states that cause delays and technology to achieve deterministic latency

In an embodiment, a power management controller is to receive thread information from a scheduler, where the thread information includes thread priority information for a thread scheduled to a core of a multicore processor. The power management controller is further to receive power consumption information from a power controller and to determine a power management action to be taken by the power controller on at least one core based at least in part on the thread priority information. Other embodiments are described and claimed.

Thread aware power management

Methods, apparatuses and storage medium associated with migration between processors by a computing device are disclosed. In various embodiments, a portable electronic device having an internal processor and internal memory may be attached to a dock. The dock may include another processor as well other memory. The attachment of the dock to the portable electronic device may cause an interrupt. In response to this interrupt, a state associated with the internal processor may be copied to the other memory of the dock. Instructions for the computing device may then be executed using the other processor of the dock. Other embodiments may be disclosed or claimed.

Execution context migration method and apparatus

One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

System and method to increase availability in a multi-level memory configuration

An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.

Handling of error prone cache line slots of memory side cache of multi-level system memory

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Providing state storage in a processor for system management mode

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved regions of a plurality of non-volatile memory modules, the respective reserved regions of the non-volatile memory modules being separate from respective host-visible regions of the non-volatile memory modules. Disclosed example methods also include configuring, with the power control unit, an information storage architecture based on the first information. Disclosed example methods further include storing, with the power control unit, second information in one or more of the respective reserved regions of the non-volatile memory modules in accordance with the information storage architecture.

Utilization of non-volatile random access memory for information storage in response to error conditions

Growing community of inventors

Olympia, WA, United States of America

Robert Charles Swanson