International Business Machines Corporation

Other

Freescale Semiconductor,inc.

Robert Charles Podnar

Jose Melanio Nunez

Marie Jeannette Sullivan

Srinath Audityan

James Andrew Welker

Thomas Albert Petersen

In response to a clock cycle and a pending READ command for data with a variably recurring access latency, a clock cycle count is adjusted. If a latency value has not been locked and if the READ command is a first READ command, the clock cycle count is stored as a locked latency value upon receiving a synchronized data available event (DQS for instance). Each subsequent READ command has an associated clock cycle count to enable pipelining wherein the clock cycle count for each READ starts incrementing when the individual READ command is issued. For subsequent READ commands, if the cycle count compares favorably with the locked latency value, data can be sampled safely from the interface at the identical latency for every READ request issued. The locked latency value can be read and/or written by software/hardware such that the read latency is consistent across multiple devices for reproducibility during debug.

Automatic READ latency calculation without software intervention for a source-synchronous interface

A computer system including a first multiprocessor system connected to a system bus and adapted to forward first and second load requests to the system bus where the first load request precedes the second load request. The system further includes a second multiprocessor system connected to the system bus. The second multiprocessor system includes a memory subsystem comprised of first and second cache levels arranged such that an operation that retrieves data from the first cache level is arbitrated through the second cache level before the data becomes available to the system bus. A snoop control state machine of the second multiprocessor system is adapted to stall arbitration of a second operation initiated in the second cache level responsive to the second load request until a first operation initiated in the first cache level responsive to the first load request has been arbitrated through the second cache level. In other words, new operations to a lower cache level are stalled until older operations pass the common arbitration point. The second multiprocessor is preferably adapted to send a data ready signal to the first multiprocessor when data associated with the first load request is available for transmission over the system bus.

Intervention ordering in a multiprocessor system

A queuing apparatus associated with a processor includes at least one static queue (,), an index generator (,), at least one index queue (,), and a static queue accessing arrangement. Each static queue (,) has a number of static queue locations (,), each for storing a static queue entry and an availability indicator (,) for indicating an availability status of the respective static queue location. The index generator (,) uses information from the static queue (,) to provide a unique index value for each static queue entry, the index value for a particular static queue entry identifying the static queue location (,) containing the particular static queue entry. Each index queue (,) has a number of index queue locations (,), each for storing one of the index values provided by the index generator (,). The static queue accessing arrangement retrieves a selected index value from a particular index queue location (,), and uses the selected index value to retrieve the static queue entry with which the selected index value is associated. Multiple index queues (,) facilitate prioritization of static queue entries, and reprioritization by transferring index queue values from one index queue to another. The index queues (,) also facilitate compaction of unnecessary static queue entries.

Static queue and index queue for storing values identifying static queue locations

Each processor (,) in a multiple processor system (,) includes a contingent response unit (,). Each contingent response unit (,) includes a pending operation unit (,) for identifying each pending address bus operation from the respective processor which specifies an address matching a snoop address from another processor. A snoop pipeline is associated with the pending operation unit (,) and includes a plurality of pipeline stages (,). Each snoop pipeline stage (,) has a contingent response flag location (,) and an identifier location (,). When a pending operation from the processor specifies an address which is matched by a younger operation from another processor, a contingent response flag control arrangement uses information from the pending operation unit (,) to set a contingent response flag in a first snoop pipeline stage (,). The contingent response flag control also stores in the first snoop pipeline stage (,) an identifier for the matched pending operation. If the matched pending operation finishes the address bus pipeline unsuccessfully and is itself retried, the contingent response flag control arrangement clears the contingent response flag in the snoop pipeline stage (,) in which the flag then resides. Otherwise the contingent response flag is used to provide a snoop response to the younger operation which matched the pending operation.

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Austin, TX, United States of America

Robert Charles Podnar