Square D Company

Robert Charles Mason

Rodney B Washington

A circuit for efficiently time-sharing the output and input configuration of a microprocessor I/O pin. The circuit includes a microprocessor having at least one I/O pin which can be selectively reconfigured for either output or input functions, a pull-up resistor, a dropping resistor and an output device. The pull-up resistor, dropping resistor and output device each have a common electrical connection at a terminal connected to the selected I/O pin. The pull-up resistor also has a terminal connected to the regulated power supply (Vcc) of the circuit. An input device or configuration switch, which is selectable between a first state and a second state, has one terminal connected to the dropping resistor and a second terminal connected to a point of the circuit at ground potential. The selected I/O pin is normally configured as an output pin for controlling the output device. At one or more intervals, as determined by a software program, the selected I/O pin will be reconfigured for input and will read the status of the input device. The input device will have provide a logical condition &ldquo;1&rdquo; or a logical condition &ldquo;0&rdquo; input status to the selected I/O pin depending on its selectable state of open or closed. The logical &ldquo;1&rdquo; or &ldquo;0&rdquo; is represented by a voltage level. The interval at which the selected I/O pin will be reconfigured for input is determined by both the type of output device being controlled and the type of input represented by the input device. The pull-up and dropping resistors have a resistance value ratio of 10:1 or greater. The actual resistance values are selected such that the output signal from the selected I/O pin can override the representative voltage levels of the logical conditions &ldquo;1&rdquo; or &ldquo;0&rdquo; of the input device when the selected I/O pin is configured for output.

Circuit for time-sharing of configurable I/O pins

A sensor system is disclosed. The system comprises a sensor for sensing an input between a first, minimum sensor input value and a second, maximum sensor input value. The sensor generates a sensor output signal relative to the sensor input value. The sensor is subject to offset and gain errors. The system further includes a microprocessor having first and second output signals and a signal conditioner coupled between the sensor and the microprocessor. The signal conditioner generates a first signal conditioner signal when the sensor input value equals the minimum sensor input value and generates a maximum signal conditioner signal when the sensor input value equals the maximum sensor input value. The signal conditioner includes circuitry for minimizing the sensor offset error and circuitry for minimizing the sensor gain error. The offset minimizing circuitry includes circuitry responsive to the first microprocessor signal for generating a signal substantially equal to zero when the sensor input value is at the minimum sensor value. The gain error minimizing circuit includes circuitry responsive to the second microprocessor signal for generating a signal substantially equal to the maximum signal conditioner value when the sensor input is at the maximum sensor value.

Growing community of inventors

Raleigh, NC, United States of America

Robert Charles Mason