Westcode Semiconductors Limited

Westinghouse Brake and Signal Holdings Limited

Robert Charles Irons

Michael John Evans

Howard Donald Neal

Kevin Robert Billett

A housing arrangement for a plurality of semiconductor chips ( ) is disclosed, in which each of the chips is received in a respective frame or cassette ( ), there being a first electrically conductive member ( ), having portions ( ) which are in electrical connection with one face of each of the chips and a second electrically conductive member ( ), having portions ( ) which are in electrical connection with an opposite face of each of the chips.

Housing for semiconductor chips

In a housing of a semiconductor device there are provided a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the semiconductor housing. Electrically conductive contact pin arrangements project from electrically insulated channels in the preformed sub-assembly, an inward end of each of the pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip. There is a sheet of electrically conductive material, resting on a base level of an inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of the pin arrangements. The channels and the pin arrangements are such that the pin arrangements are out of contact with the semiconductor chips when the preformed sub-assembly is not supported on a surface which interacts with the opposite ends of the pin arrangements.

Semiconductor chips encapsulated within a preformed sub-assembly

A semiconductor switching device comprises a substrate of silicon of a first conductivity type provided at a first face with a doped region of opposite conductivity type and at a second, opposite face with strips of doped material of the opposite conductivity type therein to form base regions. More highly doped segmented regions of material of the opposite conductivity type lie wholly within the lateral bounds of the strips and are aligned therewith to include in each case a first margin of width on each side towards the boundaries of a strip. Further doped regions, of material of the first conductivity type, separate the segmented regions and include in each case a second margin of width on each side towards the boundaries of a strip. The first and second margins are for metal-insulator-silicon gated channels in the material of the opposite conductivity type between the further regions and the substrate, and the surfaces of the segmented regions and the further regions are provided with a common ohmically connected contact for use as a source terminal.

Semiconductor switching device with segmented sources

A semiconductor device comprises a plurality of IGBT-like cells arranged in groups on a single wafer of silicon. Each group of cells has a unified gate structure and a unified source structure electrically insulated therefrom but physically overlying it. The gate structure of each group of cells is brought via a removable link to a single gate electrode for the whole device, so that the gate connection to any group of cells may be broken by removing the link, thus disabling the corresponding group of cells. Also, each group of cells is provided separately with a built-in controlled shunt conductance between its source structure and its gate structure.

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Wiltshire, United Kingdom

Robert Charles Irons