Broadcom Corporation

Forth Dimension Display, Ltd

Platipus Limited

Silicon Basis Ltd

Robert Charles Beat

Christopher Robert Chalmers

Mark Newsam

Jason Darren Drew

Ruiyan Zhao

Debra Jane Lefley

Gordon John Faulds

Neil Mallory

Mladen Panovic

Jedrzej Nowakowski

Robert Arthur Creber

Method, apparatuses, and systems are described to display image data to a sub-pixel within a micro-LED (mLED) display. A sub-pixel image data value is stored at the sub-pixel. The sub-pixel is turned to an ON state. A shared row counter value is provided to the sub-pixel. The shared row counter value and the sub-pixel image data value are compared at the sub-pixel. The sub-pixel is turned to an OFF state if the shared row counter value is equal to or greater than the sub-pixel image data value.

Apparatuses, systems, and methods for MicroLED (mLED) backplane architectures

Methods, apparatuses, and systems are described to display image data to a sub-pixel within a micro-LED (mLED) display. A row-based illumination period counter is used to operate sub-pixels within a row of the mLED display. An ON-state signal line and an illumination period signal line are coupled to the sub-pixels in the row. A first counter is incremented by an input clock signal and generates a first output. A second counter receives the first output and the second counter outputs, on the illumination period signal line, a second output that corresponds to an ON time for a sub-pixel. A sub-pixel mLED turns from the ON state to an OFF state when a stored sub-pixel data value is equal to or greater than the second output.

The present application relates to an improved static random access memory (SRAM) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell. The dedicated connection exhibits a greater capacitance than the read/write data node of the read/write circuit, such that the primary read mechanism of the SRAM is charge equalization. The SRAM write data connection to the read/write node of the read/write circuit, to permit data to be written to the plurality of storage cells. Write assist techniques are disclosed which assist writing of a '1' to the plurality of storage cells.

Static random access memory devices including a plurality of storage cells and a read/write circuit

A programmable logic circuit comprising a plurality of programmable logic elements and a plurality of programmable interconnect means, and memory means for storing the configuration of the logic elements and interconnect means, wherein said memory means is formed and arranged to store a multiplicity of different configurations for each said logic element.

Programmable logic fabric

First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

Method and system for fast data access using a memory array

A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential, and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

Decoder circuit

An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.

Method and system for fast memory access

A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

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Bristol, United Kingdom

Robert Charles Beat