National Semiconductor Corporation

Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Robert Callaghan Taft

Christopher Alan Menkus

Maria Rosaria Tursi

Vineethraj Rajappan Nair

Ols Hidri

Alexander Bodem

Heinz Werker

David Brian Barkin

Karim Thomas Taghizadeh Kaschani

Paul Joseph Kramer

Pier Francese

Tobias Hoehn

Michael Schultz

Mahalingam Nandakumar

Muhammad Yusuf Ali

Alan Erik Segervall

Brian Paul Brandt

Chris William Papalias

Filip Savic

Matthew Hansen Childs

Christopher A Menkus

Andreas Tuechler

Valerie Pons

Vineethraj R Nair

An example apparatus includes: first through eighth gated inverters each having inputs and outputs; a first and second inverter each having an input and an output, the output of the first inverter coupled to the input of the second gated inverter, the output of the second inverter coupled to the input of the third gated inverter; the fifth gated inverter coupled to the input of the first gated inverter and the input of the first inverter; the sixth gated inverter coupled to the input of the second inverter and the input of the fourth gated inverter; the seventh gated inverter coupled to the output of the first gated inverter and the output of the third gated inverter; the eighth gated inverter coupled to the output of the second gated inverter and the output of the fourth gated inverter; and a bus-holder circuit between the seventh and eighth gated inverter inputs.

Methods and apparatus to prevent lock-up of high-speed pseudo-differential frequency divider circuits

An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.

High speed multi moduli CMOS clock divider

An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.

Circuit overvoltage protection

An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.

Dielectric spaced diode

A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.

Circuits with low-pass filters and differential amplifiers

Clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock with active and inactive clock edges within a clock period, and signal capture circuitry to capture repetitive signal transitions at an active clock edge, based on pre-defined setup and hold times which determine a setup/hold window. Clock phase adjustment circuitry is configured to adjust clock phase so that the repetitive signal transitions occur within a signal capture window between setup/hold windows. Clock phase adjustment can be based on: aligning the clock inactive edges to the repetitive signal transitions; and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to a SYSREF timing reference control signal.

Meeting setup/hold times for a repetitive signal relative to a clock

In described examples, an electronic circuit for delaying a signal (received at an input node) includes a delay line with multiple tap locations, a tap line proximate to the delay line and coupled to an output node, and multiple groups of switches. Switches in the groups of switches are severally coupled between tap locations corresponding to the respective group of switches, and the tap line. When the signal is propagated through the delay line, a first number of the switches corresponding to a selected tap location are closed, a second number of the switches corresponding to an adjacent tap location are closed, and the signal is transmitted with a delay through the closed switches, to the tap line, to the output node. The delay includes an average, weighted using the first and second numbers, of delays corresponding to the selected and adjacent tap locations.

Delay line with selectable delay

An amplitude limiter circuit includes an inductor and a shunt circuit. The inductor has a first terminal connected to an input node. The shunt circuit is connected to a second terminal of the inductor and also is connected to a low impedance node. If an overvoltage condition forms on the input node, the shunt circuit forms an overvoltage current path from the input node, through the inductor, through the shunt circuit and to low impedance node.

Inductive isolation of capactive load in amplitude limiters

A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.

Circuit for meeting setup and hold times of a control signal with respect to a clock

A circuit including an amplifier array including an amplifier stage with M amplifiers (M&#x2265;2), connected to a resistor interpolator (interpolation order N&#x2265;2) including an input row and at least a second row, each row comprising interpolation resistors connected in series at nodes. The input row including M driven nodes connected to a respective amplifier, and connected in parallel to the second row, with at least some first-row interpolation nodes connected to corresponding second-row interpolation nodes. The resistor interpolator comprising at least one multi-row interpolation cell, with: in the input row, a driven node coupled through first and second interpolation resistors to respective adjacent first and second interpolation nodes; and in the second row, third and fourth interpolation nodes coupled through third and fourth interpolation resistors to an intermediate fifth interpolation node; and with the first and second interpolation nodes connected respectively to the third and fourth interpolation nodes.

Resistive interpolation for an amplifier array

A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control circuit to generate a control signal for each of the charge pumps. The control signal causes each of the charge pumps to be enabled, partially enabled, or disabled, and controls at least one of the charge pumps independently of the other charge pumps.

System and method for distributed regulation of charge pumps

A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage, a charge pump, and a cross-coupling circuit. The charge pump includes a first a first capacitor to charge while a first clock signal is high and a second capacitor to charge while a second clock signal is high. Each of the capacitors has a top plate node, a bottom plate node, a ground node, and an intermediate node between the bottom plate node and the ground node. The cross-coupling circuit couples the intermediate node of the first capacitor to the supply node while the second clock signal is high and couples the intermediate node of the second capacitor to the supply node while the first clock signal is high.

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Munich, Germany

Robert Callaghan Taft