Digital Equipment Corporation

Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Other

Intel Corporation

Compaq Information Technologies Group, L.p.

Robert C Rose

Larry D Seiler

James L Pappas

Matthew James Adiletta

Samuel William Ho

King-Wai Chow

William Ralph Wheeler

Michael D Leis

Duane E Galbi

Jash Patel

Ned C Forrester

Subramania Sudharsanan

James Ignowski

Sean M Welch

Thomas C Furlong

Mondira D Pant

Rex Petersen

Aaron M Barton

Pablo Lopez

Methods and systems to detect droop events on-chip, which may include a sensor circuit located adjacent to a voltage node to convert a corresponding voltage to a digital count or value indicative of the voltage. The sensor circuit may include an n-stage ring oscillator and an asynchronous counter. The sensor circuit may include circuitry to capture and convert a phase associated with a count to a binary fractional value to increase voltage resolution. Multiple counts associated with the node may be evaluated at the node to identify minimum and maximum counts and corresponding time stamps. More complex evaluation and control circuitry may be shared amongst a plurality of sensor circuits and may include circuitry to generate and compare counts to one or more variable thresholds, circuitry to average counts over time, and memory to store state values associated with the sensors.

Methods and systems to detect voltage changes within integrated circuits

An apparatus and method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantification values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipe lining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and therefore provide a more appealing output image.

Method and apparatus for compressing a video image

A method and system for compressing video data in a computer has video processing that is distributed between preprocessing hardware in a video capture/controller card and a central processing unit of the computer. Frames of video data are passed to a motion estimation unit of the preprocessing hardware. This unit generates motion information describing inter-frame changes in the video data. Next, motion-compensated temporal filtering is performed on the frames of video data using the motion information. A video frame processing unit of the controller card, used for processing video data to the monitor, is reused for the temporal filtering of the input video data. Finally, the temporally-filtered video data is passed to the central processing unit, which performs inter-frame and/or intra-frame compression with reference to the motion information. In this way, motion-compensated temporal filtering is performed, thus removing the associated noise without adding to the CPU's processing burden, but the costs associated with dedicated compression hardware are avoided by relying on the video capture capabilities in the video controller card.

Method and system for distributed video compression in personal computer architecture

An apparatus and method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and therefore provide a more appealing output image.

Method and apparatus for performing two pass quality video compression through pipelining and buffer management

A method of assigning quantization values for use during the compression of images is disclosed. The method includes constructing a non-parametric model during a training phase based on relationships between image characteristics, quantization values, and required bit resources to encode images. The model is built by considering a wide sample of images. The consideration includes determining the temporal and spatial characteristics of the images, compressing the images over a range of quantization values, and recording the resultant required bit resource on a per characterization/quantization level basis. Once built, the model may be used during real time compression by determining the characteristics of the input image and using the allocated resource to find a corresponding match in the non-parametric model. The associated quantization value is then assigned to the input image.

Method for choosing rate control parameters in motion-compensated transform-based picture coding scheme using non-parametric technique

An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and thereby provide a more appealing output image.

Method and apparatus for performing two pass quality video compression

This invention allows each of a plurality of windows to use its own distinct datatype and format while more than one window is being displayed on a monitor screen of a computer video graphics system. Different windows can use full color or pseudocolor frame buffer organizations, can use overlay planes or not, and can have other differences in the interpretation of the pixel values without affecting each other. Window dependent pixel datatypes are provided by means of a lookup table that is contained in logic between the frame buffer and the colormap/DAC that drives the monitor. This lookup table contains descriptors for pixel datatypes. It is indexed by a window number that is specified for each pixel. The pixel datatype descriptor accessed at each pixel is then used to control logic that processes that pixel value to create an index for the colormap. This allows each window to specify its own pixel datatype and format, that is used to interpret the pixels contained in the window.

Window dependent pixel datatypes in a computer video graphics system

A method and a device for distinguishing which pixels are to be displayed in a set of overlapping, rectangular windows in video graphics display are provided. Windows are specified as a priority ordered list of rectangles or other shapes, so that each window is computed as being visible at those pixels that are inside its rectangle but outside the rectangles of all higher priority windows. The number of rectangles required is equal to the number of rectangular windows, irrespective of the degree of overlap.

Apparatus and method for specifying windows with priority ordered

A circuit for generating an N by M pixel sprite cursor having edge extension features which are clipped to only appear in preselected windows on a video display. The circuit provides edge extension by extending the pattern appearing in the pixels located along the four edges of the sprite cursor towards the corresponding boundaries of the display. The circuit clips the cursor to preselected windows by determining on a pixel-by pixel basis which window owns the pixel to be displayed and whether the window will permit a cursor to appear in it.

Sprite cursor with edge extension and clipping

Pixel formats and a pixel mapping unit for use in a computer graphics terminal which provides an address input to a color look-up table. The disclosed pixel formats can be used to conserve frame buffer memory, color table memory, or both. For example, the formats support pseudo color or full color mapping, overlay planes, and color table bank select while using a minimum amount of memory. A valid plane feature is also supported, which can be used to enable rapid clearing of a window. The pixel mapping unit is especially handy in supporting multiple windows, because a unique mapping configuration word, which specifies how pixels are to be interpreted, may be specified for each window.

Pixel data formatting

A method and apparatus for updating the copies of state table values of a video data path chip set for a computer graphics system is provided. The apparatus uses off screen bitmap memory or other dual-ported memory in a frame buffer to store a shadow copy of the state that is stored in the video data path chips. The state tables include such things as color lookup tables, window definitions and cursors. A semaphore is used to prevent screen glitches caused by updating state tables from the copy of state table values that are partially modified. The state tables are loaded into the chips during vertical retrace, when the screen is being blanked. Before the CPU begins to update the shadow copy in the frame buffer, it claims the semaphore. If a vertical retrace occurs before the CPU has completed updating the frame buffer, the chips are not loaded during that vertical retrace. Before the chips start loading, a system timing chip claims the semaphore. The CPU cannot commence modifying the frame buffer until the load is finished.

Semaphore controlled video chip loading in a computer video graphics

A video display system for a computer graphics workstation expands the color look-up table external to the video digital-to-analog (DAC) chip by providing, for each color, a bank of one or more color look-up table extender chips. The extender chips for a given color are connected in series and the banks are connected in parallel between the frame buffer and the video DAC chip. On a pixel-by-pixel basis, and for each color channel, one of the look-up tables afforded by the extender chips or the video DAC chip is accessed using an index from the frame buffer.

Extendable-size color look-up table for computer graphics systems

This invention adds a window dependent base value to the pixel values read from a frame buffer or other source of pixel values. The base value points to the base of the colormap for that window, which is allocated within a larger, physical colormap. Each window can access physical colormap entries starting at its base value and extending up to the base value plus the maximum pixel value used in that window. Adding a window dependent base value to the pixel values for each window allows different windows to use different colormaps, each of which can be allocated to any contiguous set of entries in the physical colormap. Each window's virtual colormap need only use as many entries in the physical colormap as there are entries in the virtual colormap. Finally, virtual colormaps can be compacted or otherwise reallocated in the physical colormap without requiring changes in the pixel values stored in the frame buffer. Only the colormap base values stored for each window need be changed.

Pixel lookup in multiple variably-sized hardware virtual colormaps in a

An image generator (38) in a workstation draws its image data from a pair of frame buffers (32 and 34). The selection between the frame buffers is made by a multiplexer circuit (42) that can switch between frame buffers (32 and 34) on a pixel-by-pixel basis, i.e., different frame buffers can be used during different parts of the same scan frame of a monitor (18) in the image generator (38). A selection-signal source (46), which provides the selection signals for the multiplexer circuit (42), includes a window detector (56), which compares the outputs of counters (72 and 74) that represent the monitor scan position with the outputs of registers (62, 64, 66, and 68) that represent the boundaries of windows used by respective applications that the workstation is running. The source (46) thereby identifies the windows in which the pixel currently being displayed is located, and it employs a priority circuit (76) to identify the one such window having the highest priority. Each software application deposits in a buffer register (70) the identity of the frame buffer (32 or 34) from which the data for its display should currently be drawn, and a priority circuit generates a BUFSEL signal to identify the buffer designated by the application associated with the highest-priority window. It uses BUFSEL to control the multiplexer circuit (42). In this way, all applications do not have to switch between buffers at the same time, so the complexity and lack of flexibility imposed by synchronizing between applications is avoided.

Growing community of inventors

Hudson, MA, United States of America

Robert C Rose