Cadence Design Systems, Inc.

Other

Robert C Pack

Louis K Scheffer

Valery Axelrad

Artur P Balasinski

Aki Fujimura

Kenji Yoshida

Yoshikuni Abe

Victor Vladimir Boksha

A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Method and system for context-specific mask inspection

A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

Method and system for context-specific mask writing

A method for generating lithography marks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.

Method for creating patterns for producing integrated circuits

A method for determining device yield of a semiconductor device design, includes determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the at least one MOSFET parameter. The method provides a direct simulation link from device layout to device performance.

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Foster City, CA, United States of America

Robert C Pack