D2s, Inc.

Worldwide Pro Ltd.

Globalfoundries Inc.

Robert C Pack

Akira Fujimura

Kazuyuki Hagiwara

William Wai Yan Ho

Ryan Pearman

Sriram Madhavan

Uwe Paul Schroeder

Piyush Pathak

Wei-Long Wang

Anatoly Aadamov

Karthik Krishnamoorthy

Fadi S Batarseh

A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Method and system for dimensional uniformity using charged particle beam lithography

Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature attributes for each of the plurality of unit-level geometric constructs, annotating the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs, mapping the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane, applying a first model to the mapped hyperplane, identifying the anomalies from applying the first model, and applying a second model to the mapped hyperplane to rank the anomalies for printability risk, the generated data including rank data.

Method, system and program product for identifying anomalies in integrated circuit design layouts

A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

Method and system for critical dimension uniformity using charged particle beam lithography

A method for mask process correction or forming a pattern on a resist-coated reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle, and where the pattern exposure information is modified to lower the calculated sensitivity. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a resist-coated reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle.

A method for fracturing or mask data preparation or proximity effect correction or optical proximity correction or mask process correction is disclosed in which a set of charged particle beam shots is determined that is capable of forming a pattern on a surface, wherein critical dimension (CD) split is reduced through the use of overlapping shots.

Method and system for forming high precision patterns using charged particle beam lithography

A technique models and simulates the impact of imperfectly patterned via arrays on integrated circuits through the use of hierarchical models and a hierarchical circuit simulator. Through the hierarchical modeling and simulation approach discussed here, far more accurate electrical simulation and verification of networks is enabled for; performance, yield, and reliability. The approach further enables simulation of the effects of via process variations on large-scale circuit response. In an implementation, each via in a layout or in a via array is modeled as having an independent size from other vias based upon calibrated process simulation. The electrical characteristics of independent vias and via arrays are modeled and compiled into a reusable hierarchical distributed resistance via model. Hierarchical simulation is performed using these hierarchical distributed via models and enables more accurate results than traditional approaches.

Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits

Technique assesses the impact of physical circuit variations, specification parameter variation, or process variations on clock, signal, and power network performance and through a hierarchical modeling and hierarchical Monte Carlo simulation method.

Growing community of inventors

Morgan Hill, CA, United States of America

Robert C Pack