Wang Laboratories, Inc.

Robert C Nash

Peter A Morrison

David L Whipple

James B MacDonald

Kevin T Mahoney

Stephen W Olson

Robert R Trottier

Tom R Kibler

Andrew N Fu

Bhikoo J Patel

Apparatus and methods for performing parity checking in an environment in which devices which perform parity checking and those which do not are connected to the same synchronous bus. The bus includes a parity enable line, which carries a parity enable signal indicating that the device transmitting data on the bus is a parity device which provides the parity of the data it transmits, a parity line, which carries the parity of the data being transmitted, and a parity error line which carries a parity error signal indicating whether the receiving device detected a parity error. The data is transmitted in a first bus cycle, the parity enable signal and the parity are transmitted in the following bus cycle, and the receiving device transmits the parity error signal in the next bus cycle after that. The bus interface for each parity device includes a parity generator and logic which generates the parity and parity enable signals and receives the parity error signal when the parity device is transmitting and which receives the parity and parity enable signals and generates the parity error signal when the device is receiving. The apparatus is used with system diagnostic apparatus which records the occurrence of any parity error among devices attached to the bus.

Parity checking apparatus with bus for connecting parity devices and

An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components. The communications to SPUs all require a single SPU bus cycle; the communications to system components require one or more cycles. The system bus interface translates communications to system components into communications on the system bus and translates communications on the system bus intended for a SPU into communications to SPUs. The SPU bus includes first lines for carrying an I/O command and an identifier for an SPU involved in the communication and second lines for carrying the contents of the communication. In multicycle communications, the I/O command and identifier remain on the first lines for all cycles, but the information on the second lines varies from cycle to cycle.

I/O structure for information processing system

Growing community of inventors

Chelmsford, MA, United States of America

Robert C Nash