The Johns Hopkins University

Other

Robert C Moore

James C Fletcher

Robert E Jenkins

William S Devereux

Kim Strohbehn

Lloyd A Linstrom

Thomas R McKnight, Jr

Michael H Boehme

John R Meyer

D Gilbert Lee, Jr

Paul D Grimm

Paul R Snow

An adjustable foot rest including a base portion having a generally rectangular configuration. The base portion has a bottom wall and a top wall. The base portion includes angled opposed long side walls and angled opposed short end walls. The long side walls and the short end walls are angled outwardly from the top wall to the bottom wall. A T-shaped portion is provided having a bottom wall and a top wall. The T-shaped portion has angled interior walls and vertically disposed exterior walls. The angled interior walls are angled outwardly from the top wall to the bottom wall. The T-shaped portion adjustably couples with the base portion. At least one L-shaped portion is provided having a bottom wall and a top wall and angled interior walls and vertically disposed exterior walls. The angled interior walls are angled outwardly from the top wall to the bottom wall. The L-shaped portion adjustably couples with the base portion.

Adjustable foot rest

A small, multi-function device called the GPS/Telemetry Transmitter (GTT) that can recover telemetry (TM) data from missiles, spacecraft, balloons, or any moving platform or vehicle, and generate high accuracy trajectory estimates using GPS data is disclosed. Additionally, the concept underlying the GTT of transmitting high-data-rate telemetry and instrument data concurrently with transdigitized GPS data is incorporated in a GPS-Linked Transponder (GLT) resulting in a simpler and cheaper satellite positioning system.

Global positioning system (GPS) linked satellite and missile

Apparatus for categorizing and accumulating a plurality of different event types wherein the characteristics of each event are detected by a detector and presented to the apparatus as an electrical signal of variable analog or digital value which may indicate the type, speed, energy level or the like of an event. The apparatus includes a table look-up storage device having a plurality of individually addressable memory locations which receives the electrical or digital value and in response thereto outputs a bin address or clock select number which identifies a particular bin. Clock distribution logic circuitry receives the bin address from the look-up table storage device and in accordance with the bin address selects a particular bin and increments the event count being accumulated therein. Counter select logic circuitry is also provided for use by a host computer or the like to select a particular bin and output the event count being accumulated in the selected bin. The event count is output in a stabilized form by an output multiplexer circuit for analysis, record keeping, monitoring or the like.

Apparatus for categorizing and accumulating events

A cellular logic operation processor for performing transformations, according to a controlled sequence, of the data points of a first matrix into a corresponding number of data points of a second matrix. The processor includes a plurality of operably connected digital storage devices for temporarily and sequentially storing each neighborhood of data points from a first matrix, wherein a neighborhood of data points is comprised of a central data point and its surrounding data points in a matrix. The processor also includes a plurality of taps wherein each tap is electrically connected to a digital storage device such that the tap electrically indicates the state of the data point stored in the digital storage device. A look-up table is also provided having stored therein a plurality of transformation values which are individually addressable in accordance with the combined states indicated by the taps. The transformation value addressed in response to the combined states indicated by the taps is output by the processor as the transformation value of the central data points of the currently stored neighborhood.

Cellular logic processor

An open loop digital frequency multiplier with a multiplied output synchonized to low frequency clock pulses. The system includes a multi-stage digital counter which provides a pulse output as a function of an integer divisor. The integer divisor and the timing or counting cycle of the counter are interrelated to the frequency of a clock input. The counting cycle is controlled by a one-shot multivibrator which, in turn, is driven by a reference frequency input.

Growing community of inventors

Laurel, MD, United States of America

Robert C Moore