Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

Robert C Miller

Jian-Kuo Shen

Theodore R Staplin, Jr

John J Bradley

Ming T Miu

David B O'Keefe

Thomas O Holtey

Richard L King

Richard A Lemay

Thomas F Joyce

George J Barlow

William E Woods

James W Keeley

Richard P Kelly

Gary J Goss

Kin C Yu

John L Curley

Boyd E Darden

Michael D Smith

Gordon Lewis Steiner

Llewelyn S Dunwell

Marc C Vogt

Robert V Ledoux, Deceased

The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

Recovery method and apparatus for a pipelined processing unit of a

In a data processing system having a plurality of tightly coupled data processing units connected by an asynchronous system bus, apparatus and an associated method are described for maintaining the coherency of data groups stored in instruction cache units and execution cache units. The apparatus includes a monitor unit as part of the bus interface unit, and a bus interface unit coupling each associated data processing unit to the system bus. The monitor unit receives signals, applied to the system bus, identifying data groups transferred between the memory unit and the data processing units, including those data groups originating from the bus interface unit of which the monitor unit is a component. The bus interface unit includes directories duplicating the contents of the instruction cache unit directory and the execution cache unit directory. The monitor unit, in response to signals applied to the system bus, identifies operations that can compromise the integrity of signals stored in the associated data processing unit. The monitor unit accesses the appropriate duplicate directory to determine if the address of a compromised data group validly exists in the duplicate directory. When an address is stored in the duplicate directory along with a valid signal, the valid signal is removed from both the cache directory and the duplicate directory.

Apparatus and method for data group coherency in a tightly coupled data

A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

Hardware demand fetch cycle system interface

A video generation logic for a display controller includes a precoded PROM which combines visual attributes associated with the characters of information to be displayed on the display screen to produce multiple video control signals for modifying the dot pattern generation signal which is generated in response to character information stored in a refresh memory of the display controller. Visual attribute signals are used as an address to a video attribute generation PROM to retrieve a precoded data word associated with a particular combination of video attributes and the information contained in the retrieved data word is used to provide video control signals. Some of the video control signals are combined with the dot pattern generation signal to provide a video signal which is transmitted to the display monitor which displays the character information. One of the video attribute signals is a low intensity signal, which in the case of a character not having any other visual attributes selected, would result in the character of information being displayed in a reduced intensity level on the screen of the display monitor. Before transmission to the display monitor, this low intensity signal is modified by the video attribute generation PROM as a function of the other selected video attributes.

Display video generation system for modifying the display of character

A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

Data processing system having synchronous bus wait/retry cycle

A paging apparatus for improved mapping of virtual addresses to real addresses, addressing physical devices coupled to various communication buses, and controlling flow of data. By means of an eight-bit addressing apparatus activated for certain instructions which normally can address only 256 locations, an additional 512 locations can typically be addressed by generating control signals to modify a virtual address into a real address capable of addressing the additional locations. Additionally, the apparatus can control flow of data by enabling or disabling data control apparatus.

Hardware for extending microprocessor addressing capability

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffer to effectively ignore the byte of data corresponding to the character preceding the backspace character. Still further logic is provided within the DMC IOC to prohibit the sending of special (backspace) input/output interrupts to the CPU if there are no bytes of data remaining in the input buffer.

Data processing system having data entry backspace character apparatus

A refresh memory address generation apparatus for a video display controller is disclosed wherein rows of character information stored in a display refresh memory may be relocated without requiring the reconstruction of the display information as stored in the display refresh memory. A roll register and PROMs precoded to perform modular addition and multiplication are used to generate an address used to access the display controller refresh memory such that all but one stationary row of information on the display screen may be scrolled (rolled) up. The scrolling of the information on the display screen is accomplished without requiring movement of the display information in the refresh memory, and the only rewrite of information in the refresh memory is done to blank the one row of information which is vacated.

Scrolling display refresh memory address generation apparatus

A strobe generator in a data entry input device is responsive to an input strobe signal from a keyboard system to generate a strobe signal which is not affected by electrical noise produced by electrostatically or electromagnetically induced signals in the signal lines running between the keyboard system and the data entry device input logic. An accurate output strobe signal is generated by utilizing a retriggerable logic circuit to filter out noise signals of a duration shorter than a predetermined period. The predetermined period is chosen to be less than the minimum duration of a valid input strobe signal and greater than the duration of active noise signals. The strobe generator retains the output strobe signal in the active state by use of a flip-flop until the strobe generator receives a reset signal acknowledging that the output strobe signal has been sampled by the data entry device input logic. Once set, the flip-flop will remain set and its corresponding output strobe signal remain active until reset, even if subsequent input strobe signals of less than or greater than the predetermined period are received.

Keyboard strobe generation system

A data processing system remote monitor interface includes a first device which transmits different types of time-related information signals along multiple parallel channels to a second device for reception and combination into a different number of information signal outputs. The different types of digital information signals are synchronized by the first device prior to transmission to the second device. Components in the first device, the multiple parallel channels, and the second device are selected to maintain signal synchronization by minimizing signal skew thereby eliminating the necessity for signal resynchronization in the second device. The second device includes a receiver section which has a plurality of receivers. Each receiver operates to receive only one digital information signal and to pass the received signal onto its output. The received digital information signals are then amplified by an inverting amplifier prior to being combined into a different number of information signals which are then used by the receiving device. The system accommodates the transmission of synchronized digital information without requiring the transmission of any synchronizing information signal and without requiring the resynchronization of the information signals at the second device.

Remote monitor interface

In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

Data processing system having centralized data alignment for I/O

A method and apparatus for assuring the accuracy of data received by any device in a computer system from any other device in the same computer system or from another computer system. The existing hardware of a computer system is utilized to generate a cyclic redundant check character each time a unit of data is transmitted. The cyclic redundant check character is concatenated to the right of such data transmitted. Each time that the particular data is received, the check character and the data with which it is associated, is again manipulated in the same manner as in generating the check character. If the data received is the same as the data transmitted, the result of such manipulation is zero.

Parallel generation of serial cyclic redundancy check

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

Data processing system having data multiplex control apparatus

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

Data processing system having direct memory access bus cycle

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

Growing community of inventors

Braintree, MA, United States of America

Robert C Miller