Texas Instruments Corporation

Canon Kabushiki Kaisha

Robert C Martin

Stanley C Keeney

Bernhard H Andresen

Joseph A Casasanta

Yoshinori Satoh

Kevin M Ovens

Masanori Uchidoi

Hiroshi Aizawa

Shivaling S Mahant-Shetti

Yukio Mashimo

Clive D Bittlestone

James Fred Salzman

Stephen R Schenck

Robert J Landers

Stephen C Kwan

Yoshiyuki Takishima

Alan Stephen Bass

Bobby D Strong

Richard H Womack

Michael D Cooper

Benjamin J Sloan

Earl C Wilson

Scott Weathersby, Jr

Brock Barton

A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

Fine resolution digital delay line with coarse and fine adjustment stages

A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal. ON the positive going edge of the clock signal, data is transferred from the storage node (66) to the slave storage node (80) and then latched in the latch (82) on the negative going edge of the clock signal. This results in a minimum number of inverters, thus decreasing the Clock-to-Q time.

High speed flip-flop for gate array

A BiCMOS non-inverting buffer circuit (40) with small fan-in capacitance and excellent bipolar output drive. The circuit is ideal for buffering CMOS logic gates from excessive fan-out loads. The circuit also is less complex and more silicon efficient than present buffer circuit implementations, it provides improved transient saturation charge clamping and one buffer macro in an ASIC library can provide extended drive capability to all CMOS logic gates in the library.

BiCMOS buffer circuit

A first periodic digital waveform is to be synchronized with a second periodic digital waveform obtained by propagating the first waveform through a delay path (13) having an adjustable propagation delay. In the disclosed approach, the delay of the delay path is increased, even when an edge (43) of the second waveform trails a corresponding edge (45) of the first waveform by less than one-half cycle. The delay continues to be increased until the edge of the second waveform is eventually time-shifted past the next successive corresponding edge (49) of the first waveform.

High performance digital phase locked loop

An output buffer (12) is provided for producing an output signal varying between a voltage on a first lien (22) and a voltage on a second line (36). First output circuitry (3, 4) is provided for pulling an output terminal (26) to the voltage on first line (22). Second output circuitry (6, 7) is provided for pulling output terminal (26) to the voltage on second line (36) in response to an input thereto. First feedback circuitry (2, 8) is provided for detecting a voltage spike on first line (22) and varying the input to first output circuitry (3 4) in response. Second feedback circuitry (5, 9) is provided for detecting a voltage spike on second line (36) and varying the input to second output circuitry (6, 7) in response.

Output buffer with DI/DT and DV/DT and Tri-State Control

There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from negative voltage levels to positive voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.

Translator circuit and method of operation

An integrated circuit (10) includes at least one module (12) of operation circuits and also has other operation circuitry. The module (10) has a plurality of operation circuit terminals (98) each of which is operable to be selectively coupled to an external operation circuit terminal (86) or to a respective test terminal (96) by a multiplexer (76). A plurality of peripheral cells (30-40) are provided for connection to conductors external to the chip (10). Each cell (30-40) is bidirectionally coupled to a respective test terminal (42) and is undirectionally coupled to operation circuitry (134, 142, 158, 160) of the chip (10) such that test patterns of a testing program corresponding to the module (12) may be input into selected ones of the cells (30-40). Resulting output signals may be obtained from selected ones of the cells (30-40) that will be unaffected by operation circuitry on the integrated circuit chip exterior to the module (12).

Parallel module testing

The specification discloses an input transistor (14) which is variable between high and low impedance states in response to input voltage transitions at terminal 10. An output transistor (16) is coupled to the input transistor (14) and is responsive to an input transition at terminal 10 for changing impedance states. Circuitry including a speed up transistor (44) is coupled between the input transistor (14) and output transistor (16) for applying added current to the output transistor (16) to speed the change of impedance state. The circuitry applies added current to output transistor (16) until the output voltage at terminal (18) falls below twice the base-emitter voltage of the output transistor (16).

High to low transition speed up circuit for TTL-type gates

Power-up clear circuitry includes a latch which powers-up in a preferred state. Threshold detect circuitry changes the state of the latch when the supply voltage reaches its operating value, and then switches itself off. Transient protection circuitry ensures that the latch properly powers-up in the preferred state after a supply transient which drops below the threshold voltage of the circuit devices.

Power-up clear circuitry having two thresholds

A high speed, noninverting circuit for providing an interface between transistor-transistor logic gates and Schottky transistor logic gates. In one embodiment the output of a TTL circuit is coupled through a Schottky diode to an emitter-follower whose input is Schottky clamped. The output of the emitter-follower is coupled to a constant current sink and to the cathode of a low barrier Schottky diode, the anode of which forms the STL-compatible output of the interface circuit. The present circuit thus performs a noninverting level translation with minimum propagation delay.

A high speed, non-inverting circuit for providing an interface between

A storage device for storing photographic exposure information employs a closed-loop analog-to-digital (A-D) converter circuit includes a counter and a digital-to-analog (D-A) converter. The influence of erroneous signals which are created at the output of the D-A converter when the exposure information is stored in the counter is eliminated. The D-A converter circuit employs a ladder network of coarse accuracy. The stored exposure value, however, is highly accurate because of the closed-loop nature of the A-D converter circuit. Means responsive to the stored value for operating the exposure system of the camera are disclosed.

Exposure information storage device for a photographic camera

A TTL logic circuit employing single emitter PNP input transistors instead of a multi-emitter input stage, in order to reduce loading on input drive devices. The circuit features a logic swing of 1.6 volts centered on a circuit threshold of 1.6 volts with the logic 0 and logic 1 levels being internally clamped with p-n diode junctions to prevent transistor saturation and improve transistor switching speeds over those normally obtained using Schottky diode clamping techniques. The circuit output incorporates a Darlington stage and provides a logic 1 drive capability permitting the circuit to drive a terminated signal line having a low characteristic impedance, typically 50 ohms while maintaining a logic 1 level above 2.0 volts at 25.degree. C. Use of ion implantation techniques to define the isolation, emitter and base regions as well as the p-n diode junctions permits smaller device geometries and high F.sub.T transistors capable of high speed switching.

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Dallas, TX, United States of America

Robert C Martin