Micrel, Incorporated

Advanced Micro Devices Corporation

Lucas/signatone Corporation

Robert C Lutz

Thomas S Wong

Ulrich Bruedigam

Ralph James Eddington

Lloyd B Dickson

Klaus P Piontek

In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width.

High bandwidth dual programmable transmission line pre-emphasis method and circuit

High bandwidth programmable transmission line pre-emphasis method and circuit

A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier.

High bandwidth programmable transmission line equalizer

A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

Lateral programmable polysilicon structure incorporating polysilicon blocking diode

A semiconductor-wafer chuck for heating and cooling a device-under-test includes a heat-spreader plate with a clamping surface for a semiconductor wafer. A heater is disposed within the heat-spreader plate. A chiller heat-exchanger provides for heat removal. A motion control system is used to move the chiller heat-exchanger in relation to the heat-spreader plate, and thus provide for an adjustment of the thermal resistance and thermal coupling between the two. The heater comprises electric heating elements with a variable power input, and the chiller heat-exchanger is moved sufficiently far away to prevent boiling and evaporation of a coolant disposed inside. A device-under-test temperature controller controls the device-under-test temperature by adjusting the heater power, chiller fluid temperature and/or by moving the chiller heat-exchanger in relation to the heat spreader plate.

Semiconductor wafer electrical testing with a mobile chiller plate for rapid and precise test temperature control

A two branch circuit for converting dual complementary signals characterizing emitter coupled logic to a single signal characterizing transitor-transistor logic. A two branch circuit supplies translation between ECL input signals, referenced to a voltage supply and TTL output signals, referenced to ground, using a current summing node receiving current from both branches and connected to a TTL output driver. A first circuit branch includes a feedback loop which generates a reference current summed with the current in the second branch.

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Sunnyvale, CA, United States of America

Robert C Lutz