Intel Corporation

Robert C Lindstedt

Harry A Atwater

Robert J Walters

Maria Giorgi

Julie D Casperson

Pieter G Kik

George I Bourianoff

Daniel C Diana

Peter K Charvat

Melton C Bost

Krishnamurthy Murali

Carolyn R Duran

George I Bourlanoff

Marian E Silberstein

Maxine Fassberg

Lynn A Price

A ferroelectric polymer memory device and its method of formation are disclosed. In accordance with one embodiment, lower electrode memory device portions are formed using a damascene patterning process and upper electrode memory device portions are formed using a subtractive patterning process.

Ferroelectric polymer memory structure and method therefor

A memory device. The memory device includes a substrate and an array of nanocrystals formed proximate to the substrate. The array of nanocrystals is electrically insulated to hold charge carriers therein. A presence of charge carriers within the array of nanocrystals represents a first logic state of the memory device. An absence of the charge carriers within the array of nanocrystals represents a second logic state of the memory device. The presence and the absence of the charge carriers is determinable via directing a beam of photons onto the array of nanocrystals and sensing an optical response.

Electro-optical nanocrystal memory device

A method and apparatus for modulating light with an array of nanocrystals. First photons are directed onto an array of nanocrystals and at least a portion of the first photons ate directed by the array of nanocrystals. In one embodiment, the array of nanocrystals emit second photons. A wavelength of the second photons is modulated responsive to a signal. In one embodiment, dopants are formed proximate to the array of nanocrystals and energy from the absorbed portion of the first photons is coupled to the dopants to cause the to emit third photons. An intensity of the third photons is modulated responsive to a signal.

Nanocrystal based high-speed electro-optic modulator

A process for forming a protective polyimide layer over a semiconductor substrate includes the steps of curing a deposited polyamic acid layer at a temperature which is sufficient to reduce the etch rate of the acid layer when subsequently exposed to a developer. After formation of a photoresist masking layer over the polyamic acid, the substrate is exposed to a developer to define a plurality of bonding pad openings therein. The developer permeates into the acid layer to form a salt in the regions beneath the openings. Subsequent hardbaking imidizes the polyamic acid, but not the salt regions. Removing the photoresist layer also develops the polyimide which removes the salt regions to expose the underlying bonding pads.

Polyimide process for protecting integrated circuits

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Portland, OR, United States of America

Robert C Lindstedt