Nvidia Corporation

Google Inc.

Robert C Keller

Richard A Silkebakken

Michael C Shebanow

Brett Coon

John Stephen Montrym

Brian Keith Cabral

John R Nickolls

Roger L Allen

Benjamin J Garlick

David Brian Glasco

Karim Abdalla

Lingfeng Yuan

Ashish Gupta

Haifeng Jiang

Namit Sikka

Monica D Chawathe

Fenglin Liao

Makarand M Dharmapurikar

Matthew J P Regan

A device may store information associated with a group of items in a database. The information associated with a particular item may include a group of versions of a particular attribute. A particular version of the particular attribute may include a value associated with the particular attribute and a timestamp. The device may receive a query that specifies a time; determine that the query is associated with the particular item; and determine, based on the specified time, which version of the particular attribute is associated with the query. The device may determine which version of the particular attribute is associated with the query by identifying, based on the timestamps associated with the versions of the particular attribute, a version of the particular attribute that is a newest version, of the versions of the particular attribute that are associated with timestamps that are before or concurrent with the specified time.

Versioned database cache

A method and system for using bundle decoders in a processing pipeline is disclosed. In one embodiment, to perform a context switch between a first process and a second process operating in a processing pipeline, the first state information that is associated with the first process is placed on a connection separate from the processing pipeline. A number of decoders are coupled to this connection. The decoders obtain the first state information from a number of pipeline units on the processing pipeline by monitoring the data stream going into these pipeline units. Also, to restore the first state information after having switched out the second state information that is associated with the second process, the first state information is placed on the connection for the decoders to retrieve.

Method and system for using bundle decoders in a processing pipeline

A memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for virtualizing context memory storage and independently controlling access to the context memory without interference from other engine activities. The shared resource management unit overrides a stream of access denials (e.g., NACKs) associated with an access problem. The memory management system and method facilitate access to memory while controlling translation between virtual and physical memory 'spaces'. In one embodiment the memory management system includes a translation lookaside buffer and a fill component. The translation lookaside buffer tracks information associating a virtual memory space with a physical memory space. The fill component tracks the status of an access request progress from a plurality of engines independently and faults that occur in attempting to access a memory space.

Override system and method for memory access management

Processing units are configured to capture the unit state in unit level error status registers when a runtime error event is detected in order to facilitate debugging of runtime errors. The reporting of warnings may be disabled or enabled to selectively monitor each processing unit. Warnings for each processing unit are propagated to an exception register in a front end monitoring unit. The warnings are then aggregated and propagated to an interrupt register in a front end monitoring unit in order to selectively generate an interrupt and facilitate debugging. A debugging application may be used to query the interrupt, exception, and unit level error status registers to determine the cause of the error. A default error handling behavior that overrides error conditions may be used in conjunction with the hardware warning protocol to allow the processing units to continue operating and facilitate in the debug of runtime errors.

Hardware warning protocol for processing units

A unit status reporting protocol may also be used for context switching, debugging, and removing deadlock conditions in a processing unit. A processing unit is in one of five states: empty, active, stalled, quiescent, and halted. The state that a processing unit is in is reported to a front end monitoring unit to enable the front end monitoring unit to determine when a context switch may be performed or when a deadlock condition exists. The front end monitoring unit can issue a halt command to perform a context switch or take action to remove a deadlock condition and allow processing to resume.

Unit status reporting protocol

A context switch request is made from a host unit to a processing engine separately from the method stream to that processing engine and does not require the host unit to know what context the processing engine is currently working on. Upon receiving the request, the processing engine compares the requested context with the context that it is currently working on, and if the two are different, performs the context switch to the requested context. On the other hand, if the two are the same, the engine does not perform the context switch and continues working on the current context.

Context switch signaling method and system

In a processing pipeline having a plurality of units, an interface unit is provided between a first, upstream pipeline unit that needs to be drained prior to a context switch and a second, downstream pipeline unit that might halt prior to a context switch. The interface unit redirects data that are drained from the first pipeline unit and to be received by the second pipeline unit, to a buffer memory provided in the front end of the processing pipeline. The contents of the buffer memory are subsequently dumped into memory reserved for the context that is being stored. When the processing pipeline is restored with this context, the data that were dumped into memory are retrieved back into the buffer memory and provided to the interface unit. The interface unit receives these commands and directs them to the second pipeline unit.

Halt context switching method and system

A system includes a graphics processing unit with a processor responsive to a debug instruction that initiates the storage of execution state information. A memory stores the execution state information. A central processing unit executes a debugging program to analyze the execution state information.

Apparatus and method for debugging a graphics processing unit in response to a debug instruction

A system has a graphics processing unit with a processor to monitor selected criteria and circuitry to initiate the storage of execution state information when the selected criteria reaches a specified state. A memory stores execution state information. A central processing unit executes a debugging program to analyze the execution state information.

Apparatus and method for monitoring and debugging a graphics processing unit

A halt sequencing protocol permits a context switch to occur in a processing pipeline even before all units of the processing pipeline are idle. The context switch method based on the halt sequencing protocol includes the steps of issuing a halt request signal to the units of a processing pipeline, monitoring the status of each of the units, and freezing the states of all of the units when they are either idle or halted. Then, the states of the units, which pertain to the thread that has been halted, are dumped into memory, and the units are restored with states corresponding to a different thread that is to be executed after the context switch.

Context switching using halt sequencing protocol

A virtual memory system that maintains a list of pages that are required to be resident in a frame buffer to guarantee the eventual forward progress of a graphics application context running on a graphics system composed of multiple clients. Pages that are required to be in the frame buffer memory are never swapped out of that memory. The required page list can be dynamically sized or fixed sized. A tag file is used to prevent page swapping of a page from the frame buffer that is required to make forward progress. A forward progress indicator signifies that a page faulting client has made forward progress on behalf of a context. The presence of a forward progress indicator is used to clear the tag file, thus enabling page swapping of the previously tagged pages from the frame buffer memory.

Growing community of inventors

Palo Alto, CA, United States of America

Robert C Keller