Intel Corporation

Robert C Glenn

Michael W Altmann

Neil P Kelly

Sumant Ranganathan

Ken Drottar

Richard S Jensen

Chamath Abhayagunawardhana

David W Cline

Chuc K Thanh

Davied S Dunning

Edward S Milligan

Apparatus, systems and methods for image sensor leakage and dark current compensation are disclosed. In one implementation, a system comprises an imaging device including imaging pixels and two or more dark pixels, processing logic coupled to the imaging device, and an antenna coupled to the processing logic through an input/output (I/O) interface.

Image sensor array leakage and dark current compensation

An apparatus for providing amplified image data may include an image sensor including a number of pixel light sensing elements. Circuitry may output pixel exposure signals and a dark level signal. The differences between the pixel exposure signals and the dark level signal are uni-polar signals. A variable gain amplifier may shift the uni-polar signals to bipolar signals centered around zero, and may also amplify the bipolar signals. In this manner, a full scale output range of the variable gain amplifier may be substantially utilized.

Bi-polar signaling scheme for imaging system

An arrangement for generating control signals is provided. Embodiments provides a method, apparatus, system, and machine-readable medium to generate substantially linear, analog control signals to adjust amplitude contributions of phases of a reference clock signal to facilitate interpolation of a changing phase of an interpolated clock signal with substantially analog transitions.

Voltage controller for a highly linear phase interpolator

A method that measures a skew between a data signal and a clock signal at a receiving end of a serial link and then adjusts a phase relationship between the data signal and the clock signal to reduce the skew.

Method and apparatus for skew compensation

An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a recovered clock signal for a phase interpolator-based clock recovery system. Many embodiments may interpolate a changing phase of an interpolated clock signal with substantially analog transitions.

Phase interpolator

An arrangement for a phase interpolator based clock recovery system, a phase interpolator, and a voltage controller for a highly linear phase interpolator system is provided. Embodiments comprise a method, apparatus, system, and machine-readable medium to recover a clock signal for clocked data based on a local clock signal. In some embodiments, the local clock signal may also be used to transmit the clocked data.

Phase interpolator based clock recovering

A method is described that includes sampling data at a plurality of different relative phase positions between a clock signal and a data signal. The method also includes separately adjusting both the data signal's phase position and the clock signal's phase position to change the relative phase positions between the clock signal and the data signal at which data is sampled. Circuitry capable of performing the method is also described.

Apparatus and method for communication link receiver having adaptive clock phase shifting

Some embodiments provide a plurality of capacitors coupled in parallel and a plurality of capacitor switches, each one of the capacitor switches coupled in series with a respective one of the plurality of capacitors. Also provided may be a plurality of control circuits, each of the plurality of control circuits coupled to a respective one of the plurality of capacitor switches, to generate a respective control voltage, and to independently set a respective one of the plurality of capacitor switches to the respective control voltage, and a plurality of control switches, each of the plurality of control switches to couple and to decouple a respective one of the plurality of control circuits to and from a control signal.

System to vary capacitance based on a control signal

Some embodiments provide a switch capacitor circuit to generate a first output capacitance based on a control signal, a main loop circuit to generate an output signal based on the control signal, and an oscillating circuit to generate an oscillating signal, a frequency of the oscillating signal based at least on the first output capacitance and the output signal.

PLL with swappable tuning loops

A phase interpolator interpolates between a plurality of clock phases using a plurality of switching legs coupled to a common output. Each switching leg includes a pair of differential switching transistors each having a gate and two additional terminals, one of which is coupled to said common output. The gates are coupled to respective ones of the plurality of clock phases and their complements. Tails couple the other terminals of said switching transistors to ground. Each tail made up of a plurality of transistors. A load coupling the common output to a voltage.

Phase interpolator to interpolate between a plurality of clock phases

Some embodiments provide a charge pump to output a first control signal and a second control signal based on a frequency of an oscillating signal and a reference frequency, a switch capacitor circuit to generate a first output capacitance based on the first control signal, a main loop circuit to generate an output signal based on the second control signal, and an oscillating circuit to generate the oscillating signal, the frequency of the oscillating signal based at least on the first output capacitance and the output signal.

PLL with multiple tuning loops

Some embodiments provide a plurality of capacitors coupled in parallel, a plurality of capacitor switches, each one of the capacitor switches coupled in series with a respective one of the plurality of capacitors, one or more biasing circuits to independently set each of the plurality of capacitor switches to one of a reset voltage, a first threshold voltage, and a second threshold voltage, and a plurality of control switches, each of the control switches to couple and to decouple a respective one of the plurality of capacitor switches to and from a control voltage.

A method is described that involves directing a signal through a hysteresis comparator. Then, determining if an output signal of the hysteresis comparator, in response to the signal, is an AC signal or a DC signal. Then, deactivating a signal reception unit that receives the signal if the hysteresis comparator output signal corresponds to a DC signal; or, activating the signal reception unit if the hysteresis comparator output signal corresponds to an AC signal.

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Bend, OR, United States of America

Robert C Glenn