Monolithic Memories, Inc.

Robert C Ghest

John M Birkner

Hua-Thye Chua

Hua T Chua

Shlomo Waser

A bus organized 16.times.16 (or 8.times.8) high-speed digital bus-organized multiplier/divider for high-speed, low-power operation is implemented on a single semiconductor chip. Four working registers each of 16 (or 8) bits are used in the system. These registers are a multiplier register, a multiplicand and divisor register, a first accumulator register for storing the least significant half of a double length product after a multiplication of the remainder after a division operation, and a second accumulator register which stores the most significant half of the product after a multiplication or the quotient after a division operation. A decoder is connected to the multiplicand and multiplier registers to implement the Modified Booth Algorithm and to encode the 16 (or 8) multiplier digits. The system operates to shift the multiplier number through the multiplier register to a position where the Modified Booth Algorithm encoding takes place. The Modified Booth encoder then controls the operation of multiplexer circuits to which the outputs of the multiplicand register are applied to produce successive partial products. A carry/save arithmetic logic unit operates in conjunction with the registers to cause accumulation and storage of multiplication products and division quotient/remainders in the double length accumulator registers which provide a 32 bit output number. BACKGROUND OF THE INVENTION

High-speed digital bus-organized multiplier/divider system

This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits. The encoder includes five subsections which generate a plurality of control signals. Each of the plurality of control signals is inputted into a separate one of five multiplexor circuits each of which also receives inputs representative of eight multiplicand bits in accordance with implementation of the Modified Booth Algorithm. Each of the five multiplexer circuits provides a plurality of outputs, each of the pluralities of outputs representing a separate partial product of the multiplier and multiplicand inputs. The partial products are inputted to an array of carry-save adders. The final stage of the adder network includes a carry-look-ahead adder which produces sixteen outputs which represent the product of the multiplier and the multiplicand. The multiplier includes circuitry for permitting encoding of the multiplier inputs in either binary unsigned or in two's compliment form. A multiplier mode control input controls whether the multiplier inputs are operated upon as two's compliment or as unsigned binary numbers. Similarly, a mode control input to circuitry which generates the multiplexer inputs representative of the multiplicand also controls whether the multiplicand inputs are operated upon as two's compliment numbers or as unsigned binary numbers. The mode of the multiplier inputs and multiplicand inputs can be independently controlled, so that mixed signed and unsigned representations of the multiplier and multiplicand, respectively, can be utilized.

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Saratoga, CA, United States of America

Robert C Ghest