Arris Enterprises LLC

Intel Corporation

Arris Group, Inc.

Arris Solutions, Inc.

Broadband Royalty Corporation

Ncube Corporation

Robert C Duzett

Steven R Page

Darin J Klaas

Craig B Peterson

John L Wipfli

William L Bain, Jr

Christopher E McGinnis

Jonasan C Ho

Matthew D Phillips

Sydney D Lovely

George W Cox

Mark S Myers

David G Carson

Sunil R Shenoy

Brad W Hosler

Atiq A Bajwa

M Vittal Kini

Stanley P Kenoyer

Marc I Hebert

Marc I Herbert

Kent Mason

Artur H Lederhofer

Marcos De Oliveira Camargo

Scott A Ogilvie

Methods and apparatuses are provided for reducing the number of write operations to a flash-based storage system that stores and replaces data. The storage system includes a first storage implemented using non-flash storage and a second storage implemented using flash memory. Missed data is first stored in the first storage, which can be less sensitive than flash to write operations. The missed data is stored in the flash-based second storage only after the missed data satisfies a storage management algorithm.

Data storage methods and apparatuses for reducing the number of writes to flash-based storage

Methods, systems, and apparatuses can provide a pooling architecture for video servers and network resources. The pooling architecture can be based upon allocating content object copies to two or more nodes, intelligently selecting a primary streaming resource and a failover streaming resource, and identifying and compensating for exception asymmetries in system resource demand.

Load sharing among loosely coupled or independent video servers

Methods, systems, and computer readable media can be operable to facilitate the transfer of content between two or more storage units. The transfer of content between two or more storage units can be based upon a count of the number of hits to a storage unit entry associated with the content. In embodiments, the transfer of content between two or more storage units can be further based upon a predetermined threshold associated with a period.

Multi-tier storage for delivery of services

One or more I/O channels are assigned masks of message types that may pass through the channels, and one or more fields of an outbound message are set to one or more message type. A channel mask of an I/O channel is applied to a type of the outbound message, and if the channel mask matches the type of the outbound message, the outbound message is allowed to pass through the I/O channel to a switch. The outbound message is switched to an output port, and if the channel mask does not match the type of the outbound message, the outbound message is rejected from passing through the I/O channel and the channel mask of a next I/O channel is applied to the type of the outbound message.

Virtual networks in a communication system architecture

A method of selecting a stream server of a plurality of stream servers to which to direct a content title, by (a) evaluating a cache ease-of-entry for each of a plurality of levels of a cache hierarchy for the plurality of stream servers; and (b) selecting the stream server from the plurality of stream servers to receive a content title, the selected stream server having a most favorable cache ease-of-entry over the plurality of levels of the cache hierarchy; (c) if none of the plurality of stream servers has a most favorable cache ease-of-entry over the plurality of levels of the cache hierarchy, selecting a stream server of the plurality of stream servers with a lowest miss traffic to which to direct the title; and (d) if none of the plurality of stream servers has a lowest miss traffic, selecting a stream server of the plurality of stream servers with a lowest stream traffic to which to direct the title.

Apparatus, system and method for selecting a stream server to which to direct a content title

A media server comprises a plurality of nodes each comprising a gateway, each gateway providing memory and communication of data between mass storage and I/O ports of a node, and/or providing communication of data between the node and other nodes. Each node utilizes one or more central processors. The media server comprises logic to enable the processors to manage the streaming of data from the mass storage to the I/O ports via the gateways without communicating the data between the processors and any of the mass storage, I/O ports, or gateways.

Media stream distribution system

A method for allocating content requests to a server pool includes directing a stream requesting a novel title to one of a least-busy server in a server pool and a least-miss-traffic server in the server pool; setting the server to which the novel title was directed to the requested title's preferred server; directing a stream requesting a familiar title to the title's preferred server; and directing a stream requesting a crowded title to one of a least-busy server and the least-miss-traffic server.

Switched stream server architecture

An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data processing node also includes interface logic configured to receive signals from the interconnect and to apply the signals from the interconnect to affect the content of the cache, and to receive signals from the mass storage and to apply the signals from the mass storage to affect the content of the cache. The content of the mass storage and cache of a particular node may also be provided to other nodes of the system, via the interconnect.

Cache memory for a scalable information distribution system

A parallel processor network comprised of a plurality of nodes, each node including a processor containing a number of I/O ports, and a local memory. A communication path is established through a node by comparing a target node address in a first address packet with a processor ID of the node. If node address is equal to the target node address a receive channel is allocated to the input port and a route ready command is sent over an output port paired with the input port. If the node address is not equal to the target node address, then a first unallocated output port is selected from a port vector and the address packet is forwarded to a next node over the selected output port.

Parallel processor that routes messages around blocked or faulty nodes

An I/O processor includes an execution unit (EU), a register file, an I/O bus sequencer and a local bus sequencer. The EU decodes an ACCESS instruction having a pointer to a parameter register comprised of: a number of fields for storing a sequencer code identifying one of the sequencers; a logical byte specifying a location in memory to be addressed and valid and block bits; a reply register set pointer to a register set in the register file designated to receive a reply to the ACCESS instruction; and, a length field specifying the location and length of a data block in the register file from which data is to be obtained. A data pointer is generated by taking the logical byte in the parameter register and passing it through a register set mapper to produce a register file physical address. The valid bit of the logical byte is turned off as it is translated by the register the mapper so that the bus sequencer can take control over the corresponding register set. The block bit is set upon the condition that the ACCESS instruction attempts to access a register set whose valid bit is not set, and the block bit is reset upon the condition that the task which is executing the ACCESS instruction attempts to access a register set whose block and valid bits are set.

Multi-tasking register set mapping system which changes a register set

An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers. The register-set pointers map between logical addresses used in the instructions of the tasks used to access the pointers and physical register-set addresses used to access the register. Programmed logic in each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer dynamically allocate the register sets to the sending and destination tasks.

Memory-based interagent communication mechanism

The waveform of a strobe type signal (70) is specified by two bit strings (72, 74) stored in the RAM (20), one bit string (72) denoting when the strobe is to be reset and the other (74) denoting when the strobe is to be set. The bit positions in the bit strings correspond with clock cycles (76) taken for a DRAM memory access. The bit positions are written by means of addressable registers (71) corresponding to rows (e.g. 80-87) of the RAM. A one bit in the set bit string (72) causes the signal (70) to be asserted in the corresponding clock cycle of the request. A one bit in the reset bit string causes the signal (70) to be de-asserted in the corresponding clock cycle of the request. The set and reset times are fine-tuned to a fraction of a cycle by providing a multi-bit fractional cycle index field (78) to accompany each bit string. If a two bit quarter cycle index (QCI) field is used, the boundaries of the quarter cycles are numbered from 0 to 3. 0 coincides with the first quarter cycle after the leading edge of a clock cycle and 3 coincides with the clock cycle boundary. The one bit in the set or reset bit string denotes the cycle in which a transition is to take place, while the quarter cycle index field encoding denotes the precise quarter of the cycle in which the transition takes place.

Growing community of inventors

Hillsboro, OR, United States of America

Robert C Duzett