Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Robert C Douglas

Curtis R McAllister

Henry Yu

Kent Andrew Dickey

A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code portion and a data portion; and a first chunk of said plurality of data chunks having a tag portion, wherein said tag portion includes tag information for the entire line of memory, and wherein subsequent ones of said data chunks do not include tag information.

Arrangement of data within cache lines so that tags are first data received

Embodiments of the present invention include a memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent. The memory controller includes at least one memory-controller agent, an incoming memory-transaction dispatch unit, and an outgoing memory-transaction completion unit. Each memory-controller agent has a memory-line memory controller and a memory-line coherency controller, along with a cache memory capable of caching the contents of a memory line along with coherency information for the memory line. Memory transactions are received from cacheable entities of a computer system at the incoming memory-transaction dispatch unit, and are then presented to one or more agents. If multiple memory-read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.

Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent

A hardware-based linked list queues memory transactions in a memory controller. The memory controller includes a plurality of memory controller agents. Each agent has a head flag, a tail flag, and a next agent field, thereby allowing the agents to be arranged into linked lists. Memory transactions are received from cacheable entities of a computer system at an incoming memory transaction dispatch unit via an interconnection fabric. The incoming transactions are then presented to the plurality of agents. For each incoming read transaction, one of the agents will accept the transaction. If there are pending memory read transactions for the memory line, then the accepting agent joins a linked list of agents that are queued up to access that memory line. The accepting agent drives its index out onto a bus that connects all agents. One agent in the linked list will have its tail flag set, and that agent will clear its tail flag and latch into its next agent field the index provided by the accepting agent. Also, the accepting agent will set its tail flag to indicate that it is now at the end of the linked list. When the head agent finishes a transaction, the head agent advances the list by notifying the next agent that it is now the new head agent. The old head agent then clears a valid flag, indicating that it can now accept a new transaction, and the new head agent sets its head flag.

Self-organizing hardware processing entities that cooperate to execute requests

A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory controller agents, which are coupled to each other via a series of busses, an incoming memory transaction dispatch unit, and an outgoing memory dispatch unit. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to the plurality of agents. For each incoming transaction, one of the agents will accept the transaction. Each agent is responsible for ensuring coherency and fulfilling memory transactions for a single memory line. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests. The coherency information and memory line data associated with each memory line may be cached by each agent, thereby allowing repeated requests to the same memory line to be serviced more quickly. When two or more agents are queued up to fulfill multiple memory read transactions to the same memory line, the agents cooperate by transferring the coherency information and memory line data associated with each memory line from agent to agent, thereby minimizing the need to access main memory. The agents complete memory transactions back to the cacheable entities via the outgoing memory dispatch unit.

Memory controller having separate agents that process memory transactions in parallel

A method provides for interleaved access of a contiguous logical address space formed by a plurality of memories having respective overlapping address spaces. The memories are organized into memory segments, memory segments of equal size from different memories arranged or organized into interleave groups. An initial largest interleave group is selected and a corresponding first interleave entry is generated in a table. The interleave entry maps a corresponding initial logical address space into each of the memory segments corresponding to the first interleave group. A total memory size included thus far in the table is calculated and successive next larger groups that are integer divisors of the total memory, i.e., the partial sums formed by groups selected thus far. These steps are repeated until all of the contiguous logical address space has been mapped onto the memories. A mask may be used to extract portions from a logical address to index into a table mapping the logical address space onto the memories. Another portion of the logical address includes a memory offset.

Memory address interleaving and offset bits for cell interleaving of memory

A memory system includes a main memory controller supplying data in response to transactions received by the main memory controller. A plurality of modules each include a cache memory for storing data supplied by the main memory controller. The modules request data from the main memory controller by sending module generated transactions to the main memory controller. A cache tag array includes a cache tag corresponding to each data line stored in memory, there being a one-to-one correspondence between the cache tags and the data lines. The data lines together with their associated cache tags are combined and arranged in a plurality of sequential data chunks, the cache tags included in an initial portion of the data chunks (i.e, a first sequence of bits) followed by inclusion of the data lines in a subsequent portion of the data chunks (i.e., the usable bit positions following inclusion of all of the cache tag bits.) Each of the chunks may further include appropriate ECC bits. By this arrangement, all of the cache tags are transferred between the main memory controller and the plurality of modules prior to transfer of the bits constituting the data lines so that any coherency operations may be initiated without waiting to receive the remaining data of the data line.

Growing community of inventors

Santa Clara, CA, United States of America

Robert C Douglas