International Business Machines Corporation

Quickturn Design Systems, Inc.

Robert Bryan Cook

Gregory Michael Nordstrom

Jeffrey Joseph Ruedinger

Martin W Sachs

Fernando A Luiz

Salvatore A Calta

Angelo Salvatore Grimaldi

Caryl A Thorn

A hardware design emulation system that includes one or more emulators and one or more associated run-time assist units (RTAUs). The emulator logic is a combination of user model logic, reflecting the hardware design, and non-user model logic. A handshaking controller produces a domain step signal and a model step signal. The domain step signal indicates that the emulator is entering a state for executing the next step of the logic with which it is programmed, be it user model logic or non-user model logic. The model step signal indicates that the emulator is entering a state for advancing the user model defined by the user model logic. This dual handshaking protocol enhances versatility by enabling a wide variety of RTAUs to be used, particularly in combination with one another. Also, a RTAU can, in accordance with its programming, &ldquo;skip steps&rdquo; (either model steps or domain steps) to enhance efficiency if there is a known relationship between cycles of the emulator logic and cycles of the user model. In addition, system stoppage logic efficiently alerts other RTAUs when one RTAU has caused the emulation to stop. Furthermore, the emulation system can be scaled to accommodate a greater number of RTAUs by cascading the master panels to which they are connected.

Apparatus for improving concurrent behavior modeling with emulation

A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.

Independent computer storage addressing in input/output transfers

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Poughkeepsie, NY, United States of America

Robert Bryan Cook