Motorola Corporation

Other

Hvvi Semiconductors, Inc.

Estivation Properties LLC

Semiconductor Components Industries, LLC

Xenogenic Development Limited Liability Company

Hvvi Seminconductors, Inc.

Robert Bruce Davies

Andreas A Wild

Ira G Miller

Peter J Zdebel

David F Mietus

Robert N Dotson

Lowell E Clark

Paul T Bennett

Diann M Dow

Frank L DeSomma

Frank K Baker

Vida Ilderem

Juan Buxo

Bertrand Francis Cambou

Gary Horst Loechelt

Bishnu Prasanna Gogoi

Bernard W Boland

Warren J Schultz

Eric D Joseph

E James Prendergast

Chandrasekhara Sudhama

David H Lutz

James David Burnett

Robert L Vyne

Francine Y Robb

Israel A Lesk

Robert B Jarrett

Warren L Seely

Paul W Sanders

Merit Y Hong

David L Cave

Richard D Sivan

David M Heminger

Alexander James Elliott

Jon J Candelaria

Don W Zobel

James S Caravella

Heemyong Park

Robert E Rutter

Phuong Trong Le

Lawrence S Klingbeil, Jr

James J Stipanuk

Michael W Null

Mark D Griswold

David N Okada

Robert J Johnsen

Hassan Pirastehfar

Jeanne S Pavio

Kenneth A Berringer

Steven J Adler

George B Norris

Lloyd H Hayes

Robert Lynch Hogan

Stephen J Nugent

Charles B Anderson

Iksung Lim

James E Prendergast

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Power semiconductor device and method therefor

In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

Semiconductor package structure and method

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Transistor structure having a trench drain

A handguard system for use on a rifle having a barrel and a receiver, the hand guard system includes a barrel nut having an inner surface with a threaded portion adapted to threadably engage the receiver for securing the barrel to the receiver and an outer surface, and a tubular handguard having an end. The tubular handguard is receivable about the barrel and is received about the barrel nut, engaging the outer surface thereof. REEXAMINATION RESULTS The questions raised in reexamination proceeding No. 90/008,357, filed Dec. 1, 2006, have been considered, and the results thereof are reflected in this reissue patent which constitutes the reexamination certificate required by 35 U.S.C. 307 as provided in 37 CFR 1.570(e) forreexaminations, or the reexamination certificate required by 35 U.S.C. 316 as provided in 37 CFR 1.997(e) forreexaminations.

Rifle handguard system with integrated barrel nut

A rifle with an upper receiver and a barrel attached to the upper receiver and including a bolt carrier, and operating, buffer, and cooling systems. The operating system includes a cylinder and a piston coupled to receive propelling gases from the barrel. As the piston moves between retracted and extended positions the bolt carrier is moved between closed and open positions. The bolt carrier includes a weight movable within a guide frame between rearward and forward limits. The buffer system includes a compression spring in a tube attached to the upper receiver in abutting engagement with the bolt carrier. A partially fluid filled cylinder is attached to a coil of the spring and includes a piston and shaft. The piston is formed so that fluid in the cylinder restricts movement in one direction and allows free movement in a second direction.

Rifle

Rifle handguard

A two piece upper receiver for a firearm including a first piece having a front end, a rear end, a top, and a bottom, the first piece constructed to operatively carry a bolt carrier and bolt, and to have a barrel coupled to the front end. The bottom is constructed to have a lower receiver coupled thereto. The first piece includes a backbone extending along the top between the front end and the rear end, the back bone having upwardly directed indexing surfaces. A second piece overlies the backbone and includes mating surfaces engaging the indexing surfaces, aligning the second piece with the first piece. A receiving structure is opposite the mating surfaces for receiving accessory devices mounted thereon. Fasteners fixedly attach the second piece to the first piece to form a complete upper receiver.

Two piece upper receiver for firearms

A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region () and a dielectric platform region (). A trench () is formed adjacent to a drain () of the semiconductor device to a first depth. The etch process for forming trench () etches the dielectric platform region () to a first depth. A second trench () is etched in trench () to further isolate areas in the active region (). The etch process for forming the second trench () etches the dielectric platform region () to form a support structure for the dielectric platform in the substrate. The dielectric platform, the trench (), and the second trench () is capped and sealed. The dielectric platform is made approximately planar to the major surface of the substrate by forming the support structure from the first depth to the second depth.

Transistor structure having an active region and a dielectric platform region

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Tempe, AZ, United States of America

Robert Bruce Davies