Intel Corporation

Google Inc.

Robert Bruce Bahnsen

Robert Charles Swanson

Mallik Bulusu

Vincent J Zimmer

Robert S Gittins

Robert W Cone

Madhusudhan Rangarajan

Janusz Jurski

Mariusz Oriol

Piotr Michael Kwidzinski

Pawel Szymanski

Sridharan Sakthivelu

Mariusz Stepka

Babak B Nikjou

Piotr Sawicki

Kanivenahalli Govindaraju

William J O'Sullivan

Michael A Rothman

Narayan Ranganathan

Palsamy Sakthikumar

Yan Mayster

Brian Daniel Shucker

David N Lombard

Vikram A Saletore

Matthew E Tolentino

Krishnaswamy Viswanathan

Gerrit Saylor

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for adjusting physical location usage for a plurality of particular locations. Methods can include obtaining a three-dimensional (3D) representation of the given geographic area, wherein the 3D representation depicts a view of the given geographic area from a specified viewing perspective. For the given geographic area, traffic data is obtained indicating different traffic volumes during different time periods and one or more traffic characteristics. The 3D representation is segmented into a plurality of particular locations. For each particular location among the plurality of particular locations and based on the traffic data, a viewability score is determined that indicates an aggregate amount of time that the particular location is viewable by traffic passing the different locations. Physical location usage is then adjusted based on the viewability scores for the plurality of particular locations.

Geospatially informed resource utilization

Various systems and methods for obtaining vendor information using mobile internet devices are described herein. An inquiry for a product or service is received from a user. A location for the receipt of the product or service is received. Vendor information of a vendor of the product or service proximate to the location is determined, with the vendor information including a price for the product or service, and a wait time to receive the product or service. The vendor information is then transmitted to the user.

Obtaining vendor information using mobile internet devices

Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.

Manageability redundancy for micro server and clustered system-on-a-chip deployments

Technologies for managing image discovery includes a server controller to cause a server to enter a pre-boot state. The server controller communicates with the server while the server maintains the pre-boot state to determine identification data of the server in response to a transitioning the server to the pre-boot state. The server controller identifies a boot image of the server based on the identification data of the server and associates the server with the identified boot image.

Boot image discovery and delivery

Systems and methods providing a location-aware resource locator model for facilitating communication with networked electronic devices are generally disclosed herein. One embodiment includes a resource locator using a standard Uniform Resource Locator (URL) format, but enabling identification of one or more devices based on logical location information provided in the resource locator. The resource locator may also enable identification of the one or more devices based on logical proximity information (such as a logical term indicating a location property) relative to a dynamic location. Further disclosed embodiments include uses of a hierarchical structure to define logical terms and classes for use with a resource locator, and various location determination and lookup techniques used in connection with accessing an electronic device.

Location aware resource locator

An embodiment includes a secure and stable method for sending information across a compute continuum. For example, the method may include executing an application (e.g., video player) on a first node (e.g., tablet) with a desire to perform 'context migration' to a second node (e.g., desktop). This may allow a user to watch a movie on the tablet, stop watching the movie, and then resume watching the movie from the desktop. To do so in a secure and stable manner, the first node may request security and performance credentials from the second node. If both credential sets satisfy thresholds, the first node may transfer content (e.g., encrypted copy of a movie) and state information (e.g., placeholder indicating where the movie was when context transfer began). The second node may then allow the user to resume his or her movie watching from the desktop. Other embodiments are described herein.

Trusted application migration across computer nodes

A method and device for managing hardware errors in a multi-core environment includes allocating processor cores to a main set and a spare set of processor cores. The main set of processor cores are used by an operating system, and the spare set of processor cores are dedicated to software applications. Should a processor core error occur, a processor core swap may be performed to swap a spare processor core for a failing main processor core without interrupting the execution of the operating system.

Method and device for managing hardware errors in a multi-core environment

Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete.

Atomic transactions to non-volatile memory

Methods and apparatus relating to pre-OS (pre Operating System) image rewriting to provide cross-architecture support, security introspection, and/or performance optimization are described. In an embodiment, logic rewrites a non-native firmware interface driver into a native firmware interface driver in response to a determination that sufficient space is available in an integrity cache storage device to store the native firmware interface driver. The logic rewrites the non-native firmware interface driver into the native firmware interface driver by performing one or more of its operations during operating system runtime. Other embodiments are also claimed and described.

Techniques for pre-OS image rewriting to provide cross-architecture support, security introspection, and performance optimization

In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described.

Memory state management for electronic device

In accordance with some embodiments, a single trusted platform module per platform may be used to handle conventional trusted platform tasks as well as those that would arise prior to the existence of a primary trusted platform module in conventional systems. Thus one single trusted platform module may handle measurements of all aspects of the platform including the baseboard management controller. In some embodiments, a management engine image is validated using a read only memory embedded in a chipset such as a platform controller hub, as the root of trust. Before the baseboard management controller (BMC) is allowed to boot, it must validate the integrity of its flash memory. But the BMC image may be stored in a memory coupled to a platform controller hub (PCH) in a way that it can be validated by the PCH.

Measuring platform components with a single trusted platform module

In one embodiment, a method includes initializing a portion of a computing system in a pre-boot environment using a basic input/output system (BIOS) stored in a non-volatile storage of the computing system, launching a boot manager to enable a launch of an operating system (OS) payload, and if the OS payload is not successfully launched, executing an OS payload portion and an antivirus stack stored in the non-volatile storage to restore an integrity of the mass storage. Other embodiments are described and claimed.

Providing an immutable antivirus payload for internet ready compute nodes

A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (WB-E) memory space for an application running on the processing unit. The memory management system maps the WB-E memory space to the persistent memory. The application creates WB-E data by executing an instruction to store data to an address in the WB-E memory space. The WB-E data is automatically stored in a cache associated with the processing unit in response to creation of the WB-E data by the application. In response to execution of a commit instruction by the application after the application has created WB-E data for multiple memory addresses, the memory management system automatically ensures that all of the WB-E data for the application has been saved to the persistent memory domain. Other embodiments are described and claimed.

Growing community of inventors

Boulder, CO, United States of America

Robert Bruce Bahnsen