Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Hewlett-packard Development, L.p.

Robert Bruce Aglietti

Kenneth Mark Wilson

Rajiv Gupta

Sumit Roy

Tomas G Rokicki

Thomas Lee Watson

A method for inline bus data compression and decompression is disclosed. In one embodiment, data is selected for transfer via a data bus, the data is divided into byte sized divisions of the bus width, and each byte is compressed by an individual compression engine. The data is then properly sequenced, aligned and recombined and further transmitted in its compressed state. When required to be decompressed, the compressed data is again divided into bytes of compressed data, each byte being decompressed individually, and then restored to the bus in its uncompressed form, in essence, in the reverse order of the compression process.

Method for improving inline compression bandwidth for high speed buses

The present invention, in various embodiments, provides techniques for managing memory in computer systems. One embodiment uses a memory table having entries to locate data residing in different types of storage areas, such as physical memory, hard disc, file servers, storage devices, etc. Upon a program accessing memory for a particular piece of data, the memory table translates the data's physical address to an address used to find the table entry pointing to the requested data. In one embodiment, if the data is in physical memory, then the requested data is returned to the program. However, if the data is not in physical memory and it is determined that the data will be used frequently, then the data, in addition to being returned, is also brought to the physical memory for later use. This is because accessing the data from physical memory usually takes less time than accessing the data from other storage devices.

Memory table and memory manager for use in managing memory

The present invention, in various embodiments, provides techniques for managing latencies in accessing memory of computer systems. In one embodiment, upon accessing the memory system for a piece of data used by a first process, a latency manager determines the access time to acquire the piece of data in the memory system. The latency manager then compares the determined access time to a threshold. If the determined access time is greater than the threshold, the latency manager triggers an interrupt for the operating system to switch threads or processes so that execution of the first process is postponed and execution of a second process starts. Various embodiments include the latency manager is polled for the access time when the processor is stalled, the latency manager triggers a process switch when a particular memory subsystem is accessed, etc.

Managing latencies in accessing memory of computer systems

The present invention pertains to a system for performing data compression/decompression. The system may have a memory controller with compression/decompression logic. A first memory array may be coupled to the memory controller via a first bus and a second memory array may be coupled to the memory controller via a second bus. The system may also have logic for directing the transfer of data from the first memory array via the first bus to be processed by the compression/decompression logic and then transferred to the second memory array via the second bus.

System for compressing/decompressing data

The present invention, in various embodiments, provides techniques for managing memory in computer systems. In one embodiment, each memory page is divided into relocation blocks located at various physical locations, and a relocation table is created with entries used to locate these blocks. To access memory for a particular piece of data, a program first uses a virtual address of the data, which, through a translation look-aside buffer, is translated into a physical address within the computer system. Using the relocation table, the physical address is then translated to a relocation address that identifies the relocation block containing the requested data. From the identified relocation block, the data is returned to the program.

Relocation table for use in memory management

A processor having one or more address translation registers for holding translation information that enables translations from virtual addresses to physical addresses. The address translation registers may be allocated to a set of logical areas of a process and the logical areas may be allocated to physical pages so as to enhance a likelihood that translation information for the process will be available in the address translation registers. The address translation registers are saved and restored during context switches. The address translation registers may be used with or without translation look-aside buffers.

Processor with a general register set that includes address translation registers

A method for adding compressed page tables to an operating system is disclosed. An embodiment provides for a method in which a single entity, for example, an operating system has control of the compression and decompression of data and where the data is stored. When a data access is desired, the method accesses a table specifying the physical memory location of uncompressed data to determine if specified data is in uncompressed memory. The method of this embodiment accesses a table specifying the physical memory location of data in compressed memory to determine if the data is in the compressed memory. The method also access a page directory table to determine the location of the data in virtual memory in the event of a page fault. Then, this embodiment accesses the data based on the table look-up results.

Method and system allowing a single entity to manage memory comprising compressed and uncompressed data

A method and system for parallel fetch and decompression of compressed data blocks is disclosed. A method first accesses a table of pointers specifying the location of compressed data to obtain a pointer. Using the pointer, the method reads a pointer in the first block of data, the pointer specifying the location of the next block of compressed data in a chain of compressed data blocks. The method also transfers the rest of the first compressed data block to be decompressed. The method then fetches the next compressed data block using the second pointer while decompressing the first compressed data block. Using a pointer in each successive compressed data block in the chain, the method pre-fetches the next compressed data block while the previous compressed data block is being decompressed.

Method and system to pre-fetch compressed memory blocks using pointers

A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

Multi-threaded processing system and method for scheduling the execution of threads based on data received from a cache memory

A computer system with mechanisms for avoiding mapping conflicts in a translation look-aside buffer. A memory manager in the computer system allocates a virtual address to a process by determining a set of previously allocated virtual addresses for the process and selecting the virtual address such that the mapping of the virtual address to the translation look-aside buffer does not conflict with any of the previously allocated virtual addresses.

Avoiding mapping conflicts in a translation look-aside buffer

A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.

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San Jose, CA, United States of America

Robert Bruce Aglietti