Actel Corporation, Inc.

Robert Broze

Kyung Joon Han

John L McCollum

Sung-Rae Kim

Sung-Rea Kim

A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type diffusion regions; an insulating layer disposed over the charge generating layer; a charge storing layer disposed over the insulating layer; and another insulating layer disposed over the charge storing layer. A gate is disposed over the top insulting layer in the uppermost memory layer in the plurality of stacked memory layers.

Memory device with multiple memory layers of local charge storage

A method for providing redundancy in a floating charge trap device based programmable logic device includes the steps of sensing for a predetermined amount of stored charge in a first area of a floating trap devices in a floating trap device pair, and sensing for the predetermined amount of stored charge in a second area of the floating trap devices in the floating trap device pair when the charge in the stored charge in the first area in one of the floating trap devices is below the predetermined amount.

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Santa Cruz, CA, United States of America

Robert Broze