Samsung Electronics Co., Ltd.

Robert Brennan

Hongzhong Zheng

Krishna Teja Malladi

Oscar Prem Pinto

Manu Awasthi

Kyung Ho Kim

Zhan Ping

Jason Martineau

Walter Jun

Peng Gu

Chang-Eun Choi

Yang Yu

Wonchuri Zoo

Siamack Haghighi

Ian P Shaeffer

Harry Rogers

Chinnakrishnan Ballapuram

Jinhyun Kim

Ajay Sundar Raj

Mingyu Gao

Hyungseuk Kim

Steven L Shrader

Embodiments of the present invention include a drive-to-drive storage system comprising a host server having a host CPU and a host storage drive, one or more remote storage drives, and a peer-to-peer link connecting the host storage drive to the one or more remote storage drives. The host storage drive includes a processor and a memory, wherein the memory has stored thereon instructions that, when executed by the processor, causes the processor to transfer data from the host storage drive via the peer-to-peer link to the one or more remote storage drives when the host CPU issues a write command.

Mechanism to autonomously manage SSDs in an array

According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

Data management scheme in virtualized hyperscale environments

Mechanism to autonomously manage SSDS in an array

A computing accelerator using a lookup table. The accelerator may accelerate floating point multiplications by retrieving the fraction portion of the product of two floating-point operands from a lookup table, or by retrieving the product of two floating-point operands of two floating-point operands from a lookup table, or it may retrieve dot products of floating point vectors from a lookup table. The accelerator may be implemented in a three-dimensional memory assembly. It may use approximation, the symmetry of a multiplication lookup table, and zero-skipping to improve performance.

Computing accelerator using a lookup table

According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Unified addressing and hierarchical heterogeneous storage and memory

A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit receives a first command from the host device and converts the received first command to a processing-in-memory (PIM) command that is sent to the HBM device through the second interface. A time between when the first command is received from the host device and when the HBM system is ready to receive another command from the host device is deterministic. The logic circuit further receives a fourth command and a fifth command from the host device. The fifth command requests time-estimate information relating to a time between when the fifth command is received and when the HBM system is ready to receive another command from the host device. The time-estimate information includes a deterministic period of time and an estimated period of time for a non-deterministic period of time.

Host-based and client-based command scheduling in large bandwidth memory systems

Inventive aspects include An HBM+ system, comprising a host including at least one of a CPU, a GPU, an ASIC, or an FPGA; and an HBM+ stack including a plurality of HBM modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules. The logic die is configured to offload processing operations from the host. A system architecture is disclosed that provides specific compute capabilities in the logic die of high bandwidth memory along with the supporting hardware and software architectures, logic die microarchitecture, and memory interface signaling options. Various new methods are provided for using in-memory processing abilities of the logic die beneath an HBM memory stack. In addition, various new signaling protocols are disclosed to use an HBM interface. The logic die microarchitecture and supporting system framework are also described.

Intelligent high bandwidth memory appliance

An Ethernet solid-state drive (Ethernet SSD or eSSD) system and corresponding method provide improved latency and throughput associated with storage functionalities. The eSSD system includes at least one primary SSD, at least one secondary SSD, an Ethernet switch, and a storage-offload engine (SoE) controller. The SoE controller may operate in a replication mode and/or an erasure-coding mode. In either mode, the SoE controller receives a first write command sent from a remote device to at least one primary SSD. In the replication mode, the SoE controller sends a second write command to the at least one secondary SSD to replicate data associated with the first write command at the at least one secondary SSD. In the erasure-coding mode, the SoE determines erasure codes associated with the first write command and manages distribution of the write data and associated erasure codes. The SoE controller may also receive read commands, data cloning commands and data movement commands from the remote device.

Ethernet SSD system including storage offload engine (SoE) controller and ethernet switch

Example embodiments provide a disaggregated memory appliance, comprising: a plurality of leaf memory switches that manage one or more memory channels of one or more of leaf memory modules; a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link; and a management processor that responds to requests from one or more external processors for management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance.

Disaggregated memory appliance having a management processor that accepts request from a plurality of hosts for management, configuration and provisioning of memory

Embodiments of the inventive concept include computer-implemented method for shadowing one or more boot images of a mobile device. The technique can include duplicating boot images to shadow partitions in a user area of a non-volatile memory device such as a flash memory. The technique can include detecting boot image corruption, and causing a mobile device to boot from the shadow partitions. The technique can include dynamically shadowing and releasing blocks used by the shadow partitions. The technique can include boot failure recovery and bad image preservation through firmware flash translation layer (FTL) logical to physical mapping updates. Boot image corruption failures can be recovered from and/or debugged using the shadow partitions.

Growing community of inventors

Santa Clara, CA, United States of America

Robert Brennan