Advanced Micro Devices Corporation

Motorola Corporation

Other

Ncipher Corporation Limited

Mug Life, LLC

Robert Bradford Cohen

Tzu-Wei Lin

Anthony J Bybell

Frank C Galloway

Steven R Havlir

Sudherssen Kalaiselvan

Marius Evers

Leslie Zsohar

Anthony Jarvis

Donald L Tietjen

Grady L Giles

Gary R Morrison

Daniel B Reents

Charles E Nuckolls

Ashok Tirupathy Venkatachar

Robert E Garner

Oscar R Mitchell

Yui K Ho

Thomas A Clouqueur

William M Keshlear

Kristen L Mason

Randall Findley

Rajat Datta

Jennifer L McKeown

Greg North

Richard Goble

Jeffrey M Polega

Aparna Mandke

James Garrett

Eleanor Coy

Bill Kai Chiu Kwan

James Mossman

The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.

Dynamic configuration of processor sub-components

Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.

Merged branch target buffer entries

A processor employs a plurality of fetch and decode pipelines by dividing an instruction stream into instruction blocks with identified boundaries. The processor includes a branch predictor that generates branch predictions. Each branch prediction corresponds to a branch instruction and includes a prediction that the corresponding branch is to be taken or not taken. In addition, each branch prediction identifies both an end of the current branch prediction window and the start of another branch prediction window. Using these known boundaries, the processor provides different sequential fetch streams to different ones of the plurality of fetch and decode states, which concurrently process the instructions of the different fetch streams, thereby improving overall instruction throughput at the processor.

Processor with multiple fetch and decode pipelines

A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.

Processor with multiple op cache pipelines

A method, system, and computer-usable medium are disclosed for, comprising: examining pairs of samples in each leaf node of a plurality of decision trees and for each pair of samples, determining a neighbor frequency of each pair of samples as a frequency of how often such pair of samples are filtered into a particular leaf node of the plurality of decision trees and for each leaf node of the plurality of decision trees, determining a neighbor frequency of the leaf node as an average of the neighbor frequencies of the samples of the leaf node.

Systems and methods for neighbor frequency aggregation of parametric probability distributions with decision trees using leaf nodes

Techniques for performing instruction fetch operations are provided. The techniques include determining instruction addresses for a primary branch prediction path; requesting that a level 0 translation lookaside buffer ('TLB') caches address translations for the primary branch prediction path; determining either or both of alternate control flow path instruction addresses and lookahead control flow path instruction addresses; and requesting that either the level 0 TLB or an alternative level TLB caches address translations for either or both of the alternate control flow path instruction addresses and the lookahead control flow path instruction addresses.

Instruction address translation and caching for primary and alternate branch prediction paths

An information-processing method for application-specific processing of messages. A message is received. Whether the message is in a selected application format is ascertained. If not, the message is routed to a next location. If so, the message is routed to a selected application processor, processed by the processor, and routed to the next location.

Application-specific information-processing method, system, and apparatus

Direct memory access controller (DMA) ( ) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) ( ). A master DMA engine (MDE) ( ) includes a top level state machine ( ) to coordinate a context save state machine ( ), a parse state machine ( ), and a running state machine ( ). An loop control descriptor (LCD) queue ( ) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.

Direct memory access controller and method therefor

An apparatus (10) indicates a duplication of information stored in a content addressable memory (CAM 12) system at the time the information is written to the system. In the CAM system, Match line signals (Match 0-Match (N-1) are asserted when information being written to a predetermined row is identical to information previously stored in the system. However, the Match line signal associated with the predetermined row is disabled by a predetermined transistor (14, 16, 18, 20) when the row is written. Because information is simultaneously presented in parallel to other rows in the CAM system, a Match line signal is asserted if the information currently written to the predetermined row is identical to information previously written to another row in the CAM system. Any asserted Match line signal which was not disabled indicates to the user of the CAM system that two or more entries are identical in the CAM array.

Method and apparatus for indicating a duplication of entries in a

A microprocessor including unprime registers for use during normal operation, prime registers for use during interrupts, a normal register set for use during normal operation and conventional interrupt operations, an alternate register set for use during fast interrupt operations, and a memory stack. Three status bits are used to indicate that one or more fast interrupts have been initiated but not completed, that a fast interrupt is occurring but there are no other fast interrupts being processed, and that the CPU is currently processing a fast interrupt. These status bits indicate if there is a recursion jeopardy and are used to control the flow of information between the normal and alternate register sets and the memory stack in order to prevent recursion.

Method and apparatus for preventing recursion jeopardy

A modified grip panel for the handle portion of a revolver is provided with a thickened upper extremity having circular cylindrical bores that frictionally secure flanged cartridges. When attached to the revolver in the usual manner of a grip panel, the modified grip panel provides the user with readily available additional cartridges without impairing the normal function of the revolver.

Revolver grip with cartridge storage

In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed from page descriptors comprising, in part, translation tables stored in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in a lock field of the page descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.

Paged memory management unit which locks translators in translation

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Austin, TX, United States of America

Robert Bradford Cohen