Texas Instruments Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Huawei Technologies Co., Limited

Short Circuit Technologies LLC

Technische Universiteit Delft

University College Dublin

Nxp B.v.

Other

National Semiconductor Corporation

Mediatek Singapore Pte. Ltd.

Fastree 3d Bv

Stichting Imec Nederland

Equal1.labs Inc.

Samba Holdco Netherlands B.v.

Robert Bogdan Staszewski

Dirk Leipold

Khurram Muhammad

Chewn-Pu Jou

Huan-Neng Chen

Khurram Waheed

Masoud Babaie

Feng Wei Kuo

Min-Shueh Yuan

Oren E Eliezer

John L Wallberg

Lan-Chou Cho

Fuqiang Shi

Chia-Chun Liao

Chi-Hsueh Wang

Roman Staszewski

Kuang-Kai Yen

Chao-Chieh Li

Sameh Sameer Rezeq

Mina Shahmohammadi

Chih-Ming Hung

Kenneth James Maggio

Gennady Feygin

Seyednaser Pourmousavian

Feng-Wei Kuo

Nir Tal

Chao Chieh Li

Yi-Hsien Cho

Sudheer Kumar Vemulapalli

Imran Bashir

Lee Tsung Hsiung

Hsien-Yuan Liao

Frank Leong

See Taur Lee

Jie-Wei Lai

Ofer Friedman

Massoud Tohidian

Yuan Gao

Meng-Hsiung Hung

Amirhossein Ansari Bozorg

Augusto Ronchini Ximenes

Chih-Hsien Chang

Jingcheng Zhuang

Yu-Tso Lin

John Robert Long

Iman Madadi

Elida Isabel De Obaldia

Kai-Peng Kao

Renaldi Winoto

Francis P Cruise

Mahbuba Sheba

Ying Wu

Yihong Mao

Siraj Akhtar

Ang-Sheng Lin

Ran Katz

Gregory Lerner

Edoardo Charbon

Tsung-Hsiung Lee

Seyed Amir Reza Ahmadi Mehr

Yo-Chuol Ho

Kai Xu

Akshay Visweswaran

Min Park

Socrates Vamvakos

Dirk Leipol

Priyanka Kumar

Gerasimos S Vlachogiannakis

Dirk Robert Walter Leipold

Wei Yu Chen

Wen-Shiang Liao

Jayawardan Janardhanan

Ping-Ying Wang

Mark Pieter Van Der Heijden

Fulvio Spagna

Saket Jalan

Jinn-Yeh Chien

Yao-Hong Liu

Jaimin A Mehta

Feng Chen

Sushrant Monga

Zhuobiao He

Yossi Tsfaty

David Redmond

Mehmet Ipek

Vanessa Marie Bodrero

Fikret Dulger

Jianglin Du

Teerachot Siriburanon

Fabien Ndagijimana

Zhirui Zong

Wanghua Wu

Elida de-Obaldia

Manouchehr Entezari

Filippo Schembari

Roman Staszewki

Prasant K Vallur

Ken Maggio

Sandro Binsfeld Ferreira

In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Systems and methods for shielded inductive devices

The invention relates to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit being configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit being configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

Radio frequency oscillator

Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. In one example, a disclosed circuit includes a radio frequency (RF) oscillator and a power amplifier. The RF oscillator is configured to generate an RF signal. The power amplifier is configured to generate an amplified RF signal based on the RF signal. The power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.

Systems and methods for suppressing and mitigating harmonic distortion in a circuit

A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Device with a high efficiency voltage multiplier

Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.

Apparatus for optical coupling and system for communication

The invention relates to a resonator circuit, the resonator circuit comprising a transformer comprising a primary winding and a secondary winding, wherein the primary winding is inductively coupled with the secondary winding, a primary capacitor being connected to the primary winding, the primary capacitor and the primary winding forming a primary circuit, and a secondary capacitor being connected to the secondary winding, the secondary capacitor and the secondary winding forming a secondary circuit, wherein the resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode, and wherein the common mode resonance frequency is different from the differential mode resonance frequency.

Resonator circuit

A novel and useful system and method of generating quantum unitary noise using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0&#x3e; and |1&#x3e;. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. A detector circuit connected to the device outputs a digital stream corresponding to the probability of a particle of being detected. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability. The unitary noise can be used in stochastic rounding by controlling the bias applied to the barrier in accordance with a remainder of numbers to be rounded.

System and method of generating quantum unitary noise using silicon based quantum dot arrays

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Frequency generator and associated method

Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO Kis a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Compensation technique for the nonlinear behavior of digitally-controlled oscillator (DCO) gain

The disclosure relates to a radio frequency oscillator. The radio frequency oscillator includes a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode. The resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and the resonator circuit has a common mode resonance frequency at the excitation in the common mode. A first excitation circuit is configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit is configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

A resonator circuit includes a transformer comprising a primary winding and a secondary winding. The primary winding is inductively coupled with the secondary winding. A primary capacitor is connected to the primary winding. The primary capacitor and the primary winding form a primary circuit. A secondary capacitor is connected to the secondary winding. The secondary capacitor and the secondary winding form a secondary circuit. The resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode. The resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode. The common mode resonance frequency is different from the differential mode resonance frequency.

A novel and useful discrete time IIR bandpass filter is disclosed that takes advantage of clock phase reuse thereby leading to significant improvements in filtering, especially stop band rejection in comparison to prior art filters. The bandpass filter of the present invention achieves improved filtering performance without adding any additional clock phases to the circuit. In particular, reuse of the already existing clock phases increases the order and performance of the filter. The invention exploits reuse of the clock phases to provide higher order filtering along with a discrete time IIR filter design which is capable of operating at high frequency. Consequently, much better filtering is achieved and the quality factor of the filter is improved leading to sharper transition bands especially for close-in band blockers in modern 4G/5G receivers.

Discrete time charge sharing IIR bandpass filter incorporating clock phase reuse

An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.

All-digital phase locked loop using switched capacitor voltage doubler

Apparatus, circuits and methods for clock generation are disclosed herein. In some embodiments, an apparatus is disclosed. The apparatus includes: a first transistor pair electrically coupled to a pair of output nodes; a second transistor pair electrically coupled to the pair of output nodes; and an inductive unit electrically coupled between the output nodes and electrically coupled between gates of the first transistor pair. The inductive unit comprises: a first inductive element electrically coupled to one gate of the first transistor pair; and a second inductive element electrically coupled to one of the output nodes. The first inductive element and the second inductive element are configured to be magnetically coupled to each other.

Apparatus, circuits and methods for clock generation

Growing community of inventors

Delft, Netherlands

Robert Bogdan Staszewski