Globalfoundries Inc.

Globalfoundries Dresden Module One Limited Liability Company & Kg

Robert Binder

Joachim Metzger

Sven Beyer

Markus Lenski

Klaus Hempel

Richard Carter

Dina Triyoso

Elke Erben

Vivien Schroeder

Andy C Wei

Martin Trentzsch

Sven Schmidbauer

Berthold Reimer

Gerd Marxsen

Patrick Polakowski

Falk Graetsch

Johannes Mueller

Stefan Dünkel

Halid Mulaosmanovic

Boris Bayha

Hao Zhang

Structures for a ferroelectric field-effect transistor and methods of forming a structure for a ferroelectric field-effect transistor. The structure comprises a gate stack having a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer. The first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.

Structures for a ferroelectric field-effect transistor and related methods

The present disclosure provides a semiconductor device comprising a substrate, an undoped HfOlayer formed over the substrate and a TiN layer formed on the HfOlayer. Herein, the undoped HfOlayer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfOlayer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfOlayer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfOlayer.

Semiconductor device with ferroelectric hafnium oxide and method for forming semiconductor device

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material.

Methods for fabricating integrated circuits with fluorine passivation

Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (V) may be achieved in HK/MG transistor elements that are manufactured based on replacement gate electrode integrations. One illustrative method disclosed herein includes forming a first metal gate electrode material layer above a gate dielectric material layer having a dielectric constant of approximately 10 or greater. The method further includes exposing the first metal gate electrode material layer to an oxygen diffusion process, forming a second metal gate electrode material layer above the first metal gate electrode material layer, and adjusting an oxygen concentration gradient and a nitrogen concentration gradient in at least the first metal gate electrode material layer and the gate dielectric material layer.

Metal gate stack formation for replacement gate technology

Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

Methods for fabricating integrated circuits with narrow, metal filled openings

The work function of a high-k gate electrode structure may be adjusted in a late manufacturing stage on the basis of a lanthanum species in an N-channel transistor, thereby obtaining the desired high work function in combination with a typical conductive barrier material, such as titanium nitride. For this purpose, in some illustrative embodiments, the lanthanum species may be formed directly on the previously provided metal-containing electrode material, while an efficient barrier material may be provided in the P-channel transistor, thereby avoiding undue interaction of the lanthanum species in the P-channel transistor.

Work function adjustment in a high-K gate electrode structure after transistor fabrication by using lanthanum

Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning

Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure.

Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer

In a replacement gate approach, one work function metal may be provided in an early manufacturing stage, i.e., upon depositing the gate layer stack, thereby reducing the number of deposition steps required in a later manufacturing stage. Consequently, the further work function metal and the electrode metal may be filled into the gate trenches on the basis of superior process conditions compared to conventional replacement gate approaches.

Semiconductor device formed by a replacement gate approach based on an early work function metal

Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum

During a manufacturing sequence for forming a sophisticated high-k metal gate structure, a cover layer, such as a silicon layer, may be deposited on a metal cap layer in an in situ process in order to enhance integrity of the metal cap layer. The cover layer may provide superior integrity during the further processing, for instance in view of performing wet chemical cleaning processes and the subsequent deposition of a silicon gate material.

Enhancing integrity of a high-k gate stack by confining a metal cap layer after deposition

In a replacement gate approach in sophisticated semiconductor devices, a tantalum nitride etch stop material may be efficiently removed on the basis of a wet chemical etch recipe using ammonium hydroxide. Consequently, a further work function adjusting material may be formed with superior uniformity, while the efficiency of the subsequent adjusting of the work function may also be increased. Thus, superior uniformity, i.e., less pronounced transistor variability, may be accomplished on the basis of a replacement gate approach in which the work function of the gate electrodes of P-channel transistors and N-channel transistors is adjusted after completing the basic transistor configuration.

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Dresden, Germany

Robert Binder