Synopsys, Inc.

Lattice Semiconductor Corporation

Bipolar Integrated Technology, Inc.

Robert Beverly Lefferts

John Theodore Stonick

Victor Moroz

Jamil Kawa

James Lawrence Gorecki

James David Sproch

Daniel Keith Weinlader

Jianping Wen

David Andrew Yokoyama-Martin

Ravindar Mohan Lall

Skye Wolfer

James P Flynn

Junqi Hua

Shawn Searles

Richard H Steeves

William S Check, Jr

Peter C De Jong

Roland G De Jonge

Jeffrey Lee Sonntag

Ross Segelken

Christopher Scott Jones

Naveen John

Menaka Chandramohan

Luis Jose H Alves

Aaron Joseph Caffee

Amanda J Woon-Fat

Mark N Slamowitz

Neelakantan Gopalan

A system and method for providing electrical circuit design using cells with metal lines are described herein. According to one embodiment, a method includes instantiating a first parameterized cell (PCELL) into a first region of a row of an electrical circuit design. The first PCELL includes field effect transistor (FET) data representing a FET structure having a horizontal dimension and first metal track data representing a first set of adjustable parallel metal line segments extending along the horizontal dimension of the FET structure. The method also includes instantiating a second PCELL into a second region of the row adjacent to the first region. The second PCELL includes second metal track data representing a second set of adjustable parallel metal line segments. The method further includes connecting the first set of adjustable parallel metal line segments to the second set of adjustable parallel metal line segments and eliminating a connectivity short.

Electrical circuit design using cells with metal lines

In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

Method and apparatus for floating or applying voltage to a well of an integrated circuit

Systems and techniques for facilitating layout of an integrated circuit (IC) design are described. A distinct color pattern can be assigned to a set of shapes in a layout of the IC design that correspond to a net. Next, the layout of the IC design can be displayed in a graphical user interface (GUI) of the IC design tool. Some embodiments can move a diffusion region of a multigate device with respect to the location of the device contacts so that the diffusion region is aligned with respect to a set of fin tracks, wherein each fin of each multigate device is located on a fin track.

Using color pattern assigned to shapes for custom layout of integrated circuit (IC) designs

An electrostatic discharge (ESD) device implemented within a power domain to mitigate ESD events imparted from another power domain for reducing integrated circuit (IC) failures. A first power domain includes an interface where ESD events are received and an output that can impart ESD event voltages on other components. A second power domain includes an ESD device coupled to the output of the first power domain and a protected IC. In one embodiment, the ESD device includes a floating device with an input terminal coupled to the interface output. By floating the device receiving the ESD event in the second power domain, damaging ESD induced voltages are reduced. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration.

Preventing electrostatic discharge (ESD) failures across voltage domains

An electrostatic discharge (ESD) device is implemented within a power domain to mitigate imparting ESD induced voltages on other power domains for reducing integrated circuit (IC) failures. A first power domain includes an interface with a first terminal where an ESD event is received. The interface includes a second terminal coupled to a component within a second power domain. The ESD device is disposed between the first terminal and second terminal to intercept the ESD event. In one embodiment, the ESD device includes a blocking device. The blocking device operatively decouples the first terminal and second terminal in response to a trigger signal received during an ESD event. By operatively decoupling the terminals, transmission of the ESD induced voltages is substantially mitigated. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration.

Mitigating cross-domain transmission of electrostatic discharge (ESD) events

Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.

Method and apparatus for performing adaptive equalization

An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.

Pattern agnostic on-die scope

The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs a variable rate back channel, incorporated within an existing communication that does not increase or adversely impact the transmission rate of data on the communication channel.

System and method for embedding a sub-channel in a block coded data stream

A functional block under test (FBUT), comprising mixed-signal or analog circuits, can be tested by a digital test machine (DTM). A DTM sources test vectors to, and expects to receive certain vectors back from, a DUT. The DUT is a single, physically contiguous, IC upon which is integrated the FBUT, a mixed-signal generate and capture unit (MSGC) and a control system. The test vectors can include computer programs for instructing the control system on how to perform mixed-signal or analog-domain tests of the FBUT using resources of the MSGC (such as DACs and ADCs). The test vectors can also include data that effects the operation of a parameterized test procedure, where the test procedure is part of the control system. The control system, in accordance with the test procedure, uses the MSGC to perform mixed-signal or analog-domain tests of the FBUT. The FBUT can include an analog test bus.

Method and apparatus for integrated mixed-signal or analog testing

A high voltage CMOS switch circuit having an arrangement of device connections such that the individual transistor devices are substantially the same size, improving performance while reducing size and providing breakdown protection. The circuit switches a high voltage to the output based on a low voltage input. The circuit is ratio-less and self-biased, capable of operating a very low supply voltage compared to the state of the art.

High voltage CMOS switch

An embodiment of a pumped substrate system includes an oscillator, capacitive pump, comparing circuit, and a level shifter. The level shifter is coupled between the substrate and the positive input lead of the comparator and shifts the voltage level present on the substrate by a voltage Vbg. The comparator compares ground potential to the shifted substrate voltage. The oscillator, capacitive pump and comparing circuit form a negative feedback loop which operates to maintain the substrate voltage substantially equal to -Vbg. In one embodiment, the level shifter includes a band gap reference.

VBB reference for pumped substrates

An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary transistors are biased to a standby current that, in combination with the parasitic capacitances in the new cell, establishes a time constant sufficient to maintain the state of the secondary nodes during an alpha hit on the primary nodes, so that alpha immunity is achieved without added capacitance. A write boost circuit increases the current in the secondary transistors during a write operation. A memory array is formed of rows of such cells with all of the secondary emitters of each row coupled to a common emitter standby current source. The individual row emitter standby current sources are coupled together through a balanced resistor network so that the excess secondary emitter current generated during a write operation in a selected row is distributed across the non-selected rows, thereby maintaining the total secondary emitter current constant for the array.

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Portland, OR, United States of America

Robert Beverly Lefferts