International Business Machines Corporation

Robert Benjamin Gass

Michael Stephen Floyd

Yee Ja

Norman Karl James

Christoph Jaeschke

Phillip G Williams

Timothy Michael Skergan

Phong T Tran

Donato Orazio Forlenza

Orazio Pasquale Forlenza

Joshua D Friedrich

Joseph E Eckelman

Asher Shlomo Lazarus

Joshua P Hernandez

Abel Alaniz

Daniel W Cervantes

Timothy M Skergen

A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.

Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor

A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.

Internally controlling and enhancing logic built-in self test in a multiple core microprocessor

An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic path. In turn, the LBIST tests one or more timed signal transitions that are dependent upon the stabilized untimed logic path.

Providing pseudo-randomized static values during LBIST transition tests

This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

Automated system and processing for expedient diagnosis of broken shift registers latch chains

An apparatus and computer program product for driving values to 'don't care' (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Driving values to DC adjusted/untimed nets to identify timing problems

A method, system and computer program product for performing device characterization Logic Built-In Self-Test (LBIST) in an IC device. Test parameters of the LBIST are saved in a memory of the IC device, and nominal operational parameters of the IC device are used to define a signature of the LBIST. A determination whether the LBIST is passed or failed is made within the characterized IC device.

Techniques for performing a Logic Built-In Self-Test in an integrated circuit device

A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., 'signature' of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.

Techniques for logic built-in self-test diagnostics of integrated circuit devices

A method for driving values to 'don't care' (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Method for driving values to DC adjusted/untimed nets to identify timing problems

The present invention is directed to an improved method, system and apparatus for self-testing an electronic device. A scan latch used in a multi-cycle bus is uniquely operated to generate signal transitions consistent with the normal operating speed of the device. This occurs even when a normal signal transition would not otherwise occur since the multi-cycle bus normally requires a plurality of clock pulses to create such signal transition. The logical states of master and slave clocks associated with test scan logic are used to automatically cause the output of a scan latch to invert its output or switch from its previous state at each rising edge of the slave clock that is not preceded by a master or scan clock. This ensures transitions will appear at the output of the latch consistent with the operating clock speed of the slave clock, and these transitions are detected during an AC test of the device to determine the maximum operation frequency of the device even when the device contains an internal multi-cycle bus.

Method and apparatus for generating signal transitions used for testing an electronic device

An apparatus and method for optimum transparent latch placement in a macro design are provided. With the apparatus and method, a tree graph data structure is generated to represent the design wherein nodes of the tree graph data structure represent macros of the design. Each node of the tree graph data structure is augmented to include a maximum latch number and a clocking domain. Any leaf nodes of the tree graph data structure that cannot have latches placed in them, but have latch placement requirements, have their latch placement requirements added to their parent node if their parent node has more than one child node. The tree graph data structure is traversed to find the most timing critical nodes with timing requirements that have not been satisfied. A most timing critical path of these paths is identified. Intermediate nodes along this path are examined to determine if there are any latch placement requirements that must be met for the nodes. If these nodes have associated latch placement requirements, the requirements are satisfied first. Then latch placement along the critical path is performed in accordance with a one or more project specific placement rules.

Method and apparatus for optimum transparent latch placement in a macro design

A method and system for performing hamming distance comparison. A hamming distance comparator may comprise a plurality of evaluation circuits where each evaluation circuit may be configured to evaluate a bit in a received data packet. Each evaluation circuit may comprise a first and a second capacitor configured to store a true and a complement value of a bit evaluated during a reset state. During an evaluation state, one of the first or second capacitors may be switched if the state of the bit evaluated changed state in a second subsequent received data packet. By switching one of the first or second capacitors, a net change in potential may be provided on a common line coupled to the first and second capacitors. The net change in potential on the common line provided by the evaluation circuits may be used to determine the hamming distance.

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Pflugerville, TX, United States of America

Robert Benjamin Gass