International Business Machines Corporation

Sun Microsystems, Inc.

Robert Barton Garner

Winfried W Wilcke

William N Joy

Steven Alan Cordes

John E Watkins

Harald Huels

Matthew J Farinelli

Barry Jay Rubin

Claudio Fleiner

William A Shannon

Joseph F Moran

Manfred Ries

William Van Loo

Ray Cheng

Richard Michael Williams

Howard Kahn

Anant Agrawal

Donald C Jackson

Kenneth Richard Fernandez

Kwang G Tan

According to the present invention, there is provided a system for removing heat from server blades densely packaged in a rack of server blades. The system includes a liquid distribution manifold. In addition, the system includes a plurality of cold blades attached to the liquid distribution manifold, wherein liquid is circulated through the liquid distribution manifold and the cold blades. Moreover, the system includes at least one server blade attached to each of the cold blades.

Method for high-density packaging and cooling of high-powered compute and storage server blades

A flexible capacitive coupler assembly includes a flexible dielectric substrate assembly having a front surface and a rear surface, the front surface having thereon a macroscopic metal capacitive pad. A package supports the flexible dielectric substrate. An electrical connection is made to package wiring or leads on the flexible dielectric substrate to establish electrical contact with a computer subsystem.

Flexible capacitive coupler assembly and method of manufacture

A three-dimensional computer infrastructure cooling system is provided. The three-dimensional computer infrastructure cooling system includes at least one compute, storage, or communications brick. In addition, the three-dimensional computer infrastructure cooling system includes at least one coldrail to facilitate the removal of heat from the at least one compute, storage, or communications brick. Also, the three-dimensional computer infrastructure includes a brick-internal carrier within the at least one compute, storage, communications brick, wherein the brick-internal carrier is attached to the at least one coldrail. Moreover, the three-dimensional computer infrastructure includes a power dissipating electronic element within the at-least-one compute, storage, or communications brick, wherein the power dissipating element is attached to the brick-internal carrier.

System and method for providing cooling in a three-dimensional infrastructure for massively scalable computers

A mechanism that automatically achieves alignment of the communications elements during assembly of a modular computer system, without the need for human intervention. The mechanism comprises an alignment frame provided with bumps and depressions. The bumps in the alignment frames mate with the depressions on adjacent alignment frames. Each depression comprises an entrance opening that is wider than the diameter of the bumps. The diameter of the entrance opening is determined by the expected accuracy of the alignment of subsystems or bricks within the modular electronic system. When it is desired to align the communication elements, the alignment frames are brought into engagement by causing alignment guides to slide past each other, and to guide the bumps in the alignment frames into the depressions in the adjacent alignment frames. The mechanism further comprises a set of springs that force the allow the alignment frames to be retained securely by the communications elements.

Mechanism for self-alignment of communications elements in a modular electronic system

A scalable and compact computer system of three-dimensional subsystems each having capacitive couplers on its external surfaces for transmitting and receiving electrical signals to and from adjacent subsystems. Each surface having an electrically non-conducting substrate, one or more electrically conducting pads on the substrate, and electrical leads for coupling the pads to the subsystem's circuits. Two adjacent pads, each from a different subsystem, form a capacitive coupler to carry the signals between the subsystems. The pads are covered by a low-loss dielectric material having a large dielectric constant for improved signal transmission. A differential signal may be supported using two capacitive couplers to respectively carry the positive and negative signals of the differential signal. The subsystems might be replaced or left in place when they failed. Additional subsystems might be added to the system to expand its capacity.

Scalable computer system having surface-mounted capacitive couplers for intercommunication

Hardware and software improvements in workstations which utilize virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes. In virtual addressing, multi-user workstations, system performance may be improved significantly by including a virtual address write back cache as one of the system elements. Data protection and the reassignment of virtual addresses are supported within such a system as well. Multiple active processes, each with its own virtual address space, and an operating system shared by those processes in a manner which is invisible to user programs. Cache 'Flush' logic is used to remove selected blocks from the virtual cache when virtual addresses are to be reassigned.

Virtual address write back cache with address reassignment and cache

An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register window groups being physically arranged so the input registers of each group are the same physical register as the output registers of the next adjacent register window group thereby forming one large interconnected ring of register window groups, an arrangement for designating the register window group presently active, and an arrangement for designating register window groups which are not available for use.

Risc processing unit which selectively isolates register windows by

A computer system which includes a central processing unit including a first processing unit that performs basic processing functions and a co-processing unit that performs multiple specialized processing functions concurrently with the first processing unit, an arrangement for detecting the occurrence of a function causing an exception in a result produced by the coprocessing unit, an arrangement for specifying to the first processing unit any exception in a result produced by the coprocessing unit, an arrangement for using the first processing unit to implement any function which causes an exception in a result produced by the co-processing unit, an arrangement for storing the identification of the instruction being handled by the first processing unit when a function causing any exception in a result produced by the co-processing unit occurs, and an arrangement for determing the instruction which produced the exception.

Method and apparatus for executing concurrent CO processor operations

BISC with interconnected register ring and selectively operating portion

An improved interface between a processor and an external cache system, having particular application for use in high speed computer systems. A cache memory for storing frequently accessed data is coupled to a cache address register (CAR). A processor generates addresses which correspond to locations of desired data in the cache, and provides these addresses to the CAR. Upon the receipt of a clock signal, the CAR couples the address to the cache memory. The processor includes a data register for receiving accessed cache data over a data bus. Data is latched into the register upon the receipt of a clock signal. Due to inherent delays associated with digital logic comprising the processor, clock signals provided by an external clock are received by the CAR prior to their receipt by the processor's data register. This delay (a fraction of a clock cycle) provides additional time to access the cache memory before the data is expected on the data bus. The CAR is fabricated out of a technology that allows it to drive the address to the large capacitive load of the cache memory in much less time than the processor itself could drive such a load. Thus, due to this buffering capability of the CAR, the cache can be much larger than what could be supported by the processor itself. The time expended sending the address from the processor to the CAR buffer, which would otherwise not be present if the processor addressed the cache directly from an internal register, does not subtract from the processor cycle time since the processor can compute the cache address and send it to the CAR in less than the time required to access the cache.

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San Jose, CA, United States of America

Robert Barton Garner