Freescale Semiconductor,inc.

Nxp Usa, Inc.

Robert Bahary

Eric J Jackowski

Jayakrishnan Cheriyath Mundarath

Leo G Dehner

Robert Greenwood

A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.

Multi-standard low-density parity check decoder

A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. An address generator generates the regenerated interleaver sequence based on the column indexes and computed data. In embodiments the address generator can read column indexes from the addressable column index memory, compute the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data, combine the column indexes so read and the row indexes so permuted, use a row counter, and identify out of bounds addresses using the regenerated interleaver sequence.

Turbo decoders with stored column indexes for interleaver address generation and out-of-bounds detection and associated methods

A first-in first-out (FIFO) buffer system includes FIFO control logic and first and second storage partitions. Each storage partition includes a corresponding single-port memory bank and a prefetch buffer. The FIFO control logic alternates processing of PUSH commands between the first and second storage partitions. Additionally, the FIFO control logic anticipates POP commands based on the FIFO order and the alternating PUSH arrangement by initiating prefetches of data so that data to be accessed by a POP command is available at either the prefetch buffer (if the prefetch has completed) or the output of the single-port memory bank (if the prefetch has not yet completed) of the corresponding storage partition at the time the POP command is received, thereby enabling the output of the data for the POP command in the same clock cycle in which the POP command is received.

FIFO buffer system providing same clock cycle response to pop commands

A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates LLRs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. The turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle. The data can be rearranged within the words in an order format for the turbo decoder engines to later read them by providing sub-words corresponding to respective ones of the plurality of turbo decoder engines.

Turbo decoder with a low-power input format and associated method

A plurality of turbo decoder engines store extrinsic values when concurrently decoding a received signal encoded within rows and columns of an interleaving matrix where interleaved values stay in a same re-ordered row during interleaving. An extrinsic reader and extrinsic writer accesses extrinsic memories using extrinsic addresses. A deinterleaver accesses the extrinsic addressable memories by arranging storage of the extrinsic values by the same rows of the same interleaving matrix that was used to encode the received signal, each of the rows corresponding to one of the plurality of turbo decoder engines, and, in embodiments, can group the extrinsic values such that all the extrinsic values in each one of the rows of the interleaving matrix go in a same one of the plurality of the extrinsic addressable memory. The deinterleaver can skip read of extrinsic values corresponding to dummy entries in the interleaving matrix.

Turbo decoders with extrinsic addressing and associated methods

A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus () comprising a multiplier stage () having an output coupled to an input of an accumulator stage () having an accumulator feedback output () selectively coupled to an input of the multiplier stage over a plurality of clock cycles; iteratively calculating a final working loop variable z over an additional plurality of clock cycles; multiplying the final working loop variable z and a complex input vector x to compute a final multiplier value; and adding a least significant complex polynomial coefficient to the final multiplier value using the multiplier stage of the multiply and accumulate feedback apparatus to yield a result of the polynomial evaluation.

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Arlington Heights, IL, United States of America

Robert Bahary