Texas Instruments Corporation

Robert B Staszewski

Dirk Leipold

Kenneth James Maggio

Gennady Feygin

Michel Combes

A frequency synthesizer architecture naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase-domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information.

Digital phase-domain PLL frequency synthesizer

The hard disk drive includes a storage media system (,) and a read channel (,) for reading data from the storage media system (,). The read channel (,) is operable to read a preamble. Also included is a phase lock loop (,) which is coupled to the read channel (,) and operable to acquire the preamble signal. The phase lock loop (,) includes a timing gradient generator (,) which is operable to determine a timing gradient using a single term timing gradient equation. Also included is a loop filter (,), coupled to the timing gradient generator (,). The loop filter (,) determines an integral timing. A voltage controlled oscillator (,) is coupled to the loop filter (,) and determines a timing phase, the timing phase representing a timing adjustment for the read channel (,).

Method and apparatus for acquiring a preamble signal in a hard disk drive

A fast FIR filter,, a system, and a method that increases the operating speed of a filter. The system uses a high order numbering system, in particular Radix-8, and appropriate control lines, parallel data buses,and simple circuits for coefficient pre-multiplying. In a typical application, incoming high-speed unequalized 6-bit data are encoded into the high order numbering system, and placed on two data buses,, one containing the high order data bit stream, e.g., 4 bits for Radix-8, and the other the low order data bit stream, e.g., 3 bits for Radix-8. The data are further encoded in &ldquo;hot-one&rdquo; mode so that at all times exactly one bit is asserted. FIR coefficients are calculated, requiring pre-multiplication for only four non-trivial cases in the case of Radix-8 encoding: C, &minus;C, 3C, and &minus;3C, where C is a coefficient value. Because the coefficients do not change at high data rates, high-speed operation of pre-multiplication is not required. Further, by using the &ldquo;hot-one&rdquo; property incorporated in each bus, a simple low-propagational delay passgate multiplexer can be used for pre-multiplying.

Digital finite-impulse-response (FIR) filter with a modified architecture based on high order Radix-N numbering

A method for generating an updated path metric includes combining each of first and second provisional path metric first portions with an associated branch metric first portion to produce a first provisional updated path metric first portion candidate and a second provisional updated path metric first portion candidate, respectively. The method also includes selecting one of the provisional first portion updated path metric candidates to produce an updated path metric first portion candidate and combining any carry component of the selected updated path metric first portion candidate with a path metric second portion and a branch metric second portion to produce a first updated path metric second portion candidate. The method also includes comparing the updated path metric second portion candidate to at least one other updated path metric second portion candidate; and selecting one of the updated path metric second portion candidates to produce an updated path metric second portion.

Method and system for estimating an input data sequence based on an output data sequence and hard disk drive incorporating same

A system and a method for calculating a value for the &ldquo;Band Zero&rdquo; (B&empty;) contribution to the processing of a digital signal by processing the separate parts of the signal at separate times. The method increases operating speed of a feedback circuit, for example, by providing a processing path (,) that is not on the main high-speed processing path of a system such as a read channel of a disk drive. By processing the most time-consuming determination &ldquo;in parallel,&rdquo; the high-speed portion of processing is able to maintain an optimum throughput. The method also lends itself to processing in those applications where more than one mode is used. For example, when used in a read channel (,) of a disk drive (,) employing a FIR filter, three modes are desired: FIR-bypass, acquisition, and data tracking. Being able to switch easily among the three modes provided for in a read channel (,) of a disk drive (,) demonstrates the adaptability of the method and supporting structure to a broad class of feedback circuits used in systems employing high throughput rates.

High-speed digital circuit employing a band-zero-determination-aside (B&Oslash;DA) architecture

A read channel circuit (27) for a hard disk drive system (10) includes an analog-to-digital converter (38) having an output (39) which is supplied through a filter (41) to a detector (46) and to a band/error circuit (47). The band/error circuit extracts from the filter output a band value (48) and an error value (49). The band and error values are used by a timing recovery loop (51, 53) to control the operation of the analog-to-digital converter, and are used by a gain recovery loop (51, 54) to facilitate an automatic gain control function for an analog circuit (36). The band/error circuit uses targets and thresholds which are each a power of two, so that a predetermined number of the least significant bits from the output of the filter can be used as the error value, without modification. The band value is determined from the most significant bits of the output of the filter. The filter not only shapes the signal spectrum, but also performs an integer space transformation that normalizes the output of the analog-to-digital converter with respect to the predetermined targets and thresholds of the band/error circuit.

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Garland, TX, United States of America

Robert B Staszewski