Micron Technology Incorporated

Nan Ya Technology Corporation

Robert B Kerr

Luan C Tran

D Mark Durcan

Howard E Rhodes

Kirk D Prall

David F Cheffings

Christopher Murphy

Tyler A Lowrey

Fernando N Gonzalez

Sanh D Tang

Haitao Liu

Kamal M Karda

Brian M Shirley

Sangmin Hwang

Wolfgang Mueller

Sourabh Dhir

Mark A McQueen

Brent Keeth

Zhiqiang (Jeff) Wu

Shubneesh Batra

Rongsheng Yang

Jaydip Guha

Hung-Ming Tsai

Vivek Gopalan

Durga Prasanna Panda

Fernando Gonz&aacute;lez

Panda Durga

An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Array of recessed access gate lines

Array of conductive lines individually extending transversally across and elevationally over a mid-portion of individual active area regions

Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines

A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.

Memory process

Memory process and memory structure made thereby

The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.

Method of manufacturing sidewall spacers on a memory device

Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.

Methods of contacting lines and methods of forming an electrical contact in a semiconductor device

Method of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits

A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

Random access memory

An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.

Double LDD devices for improved DRAM refresh

Method of forming a semiconductor memory device

Double LDD devices for improved dram refresh

A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

Method of controlling outdiffusion in a doped three-dimensional film

Growing community of inventors

Boise, ID, United States of America

Robert B Kerr