Honeywell Information Systems Inc.

Robert B Johnson

Chester M Nibby, Jr

Edward R Salas

Edwin P Fisher

Dana W Moore

Paul S Feldman

George J Barlow

Richard A Lemay

John L Curley

Daniel A Boudreau

A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.

Pause apparatus for a memory controller with interleaved queuing

A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address. In response to signals generated by the identification sections of the installed memory boards, the decoder circuits are selectively enabled to decode those bit combinations of the address portion specified by the sections for enabling successive addressing of all of the blocks of location within the system.

Memory identification apparatus and method

A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory contiguous.

Memory system with automatic memory configuration

A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

Identification apparatus for use in a controller to facilitate the

A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which eliminates processing delays particularly in cases where such requests involve multiword transfers over successive memory cycles of operation.

Memory controller with interleaved queuing apparatus

A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit which couples to the bus is connected to increment by one the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.

Sequential word aligned addressing apparatus

Apparatus is included in a main memory subsystem of a data processing system which receives multibyte data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies the multibyte data signals together with associated parity bits for writing into an addressed storage location of memory. During the write cycle, error encoder circuits generate check code bits from the multibyte data and parity bits which are coded to signal selectively the presence of a multibyte uncorrectable error condition in accordance with the parity bits from a device. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check bits read out from an addressed location are operative to generate a number of syndrome bits. These bits have a predetermined characteristic for indicating the existence of an uncorrectable error condition when one or more data bytes were in error and there was a single bit error in memory.

Apparatus for deferring error detection of multibyte parity encoded data

A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.

Sequential word aligned address apparatus

A memory controller couples to a number of memory modules and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command from a requesting device. This command when decoded causes the controller to read out from the memory modules a predetermined number of words starting with any word boundary at the location specified by the stored address portion.

Memory controller with address independent burst mode capability

Refresh and initialize counter circuits included within a dynamic memory system are supplemented with additional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with modulus one less than a maximum count so as to generate a sequence of counts over a corresponding number of cycles of operation for selection of row and column addresses which enable the information stored in each location of the memory system to be read out, corrected for single bit errors and rewritten back thereby rendering the system less susceptible to soft errors such as those produced by alpha particles.

Soft error rewrite control system

A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command or memory request from a requesting device. This command when decoded causes the controller to read out from the memory module units a predetermined number of word pairs starting with the location specified by the stored address portion.

Memory controller with burst mode capability

A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.

Memory controller with queue control apparatus

A memory subsystem couples to a double wide word bus in common with a number of central processing units for processing memory requests received therefrom. The subsystem includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes common control circuits, timing circuits and common addressing circuits. The addressing circuits which couple to both module units provide the required address signals to both modules for enabling the simultaneous access of a pair of words therefrom into a pair of data registers. The outputs of the data registers couple to the inputs of a pair of output multiplexer circuits. The outputs of the multiplexer circuits are connected to provide double wide output to the double wide word bus. The timing circuits generate a sequence of timing signals for access and read out of the pair of words into the data registers for simultaneous transfer via the multiplexer circuits to the double wide bus. The control circuits which in response to each memory request specifying a double fetch operation, condition the multiplexer circuits and memory subsystem for operation in a degraded mode. When in this mode, the pair of words read out to the data registers are multiplexed onto a portion of the bus for transfer to the requesting central processing unit over a corresponding number of successive bus cycles thereby making the memory subsystem compatible with central processing units having a double fetch capability.

Multimode memory system using a multiword common bus for double word and

Soft error rewrite control apparatus is included within a memory system for rendering the semiconductor memory modules less susceptible to single bit errors produced by alpha particles and other system disturbances. During a number of successive memory cycles occurring at a predetermined rate, the soft error rewrite control apparatus enables the read out of information stored within each module location, the correction of any single bit errors contained therein and the rewriting of the corrected information back into such location. Diagnostic apparatus is further included which is connected to place the memory system in a state for testing and verifying the operation of the soft error control apparatus. Also, the diagnostic apparatus is connected to condition the soft error control apparatus for operating in a high speed mode enabling the read out correction and rewriting of each location to take place within a minimum amount of time. By monitoring the status of the information being corrected, the diagnostic apparatus is able to signal whether or not the soft error control apparatus is operating properly.

Method and apparatus for testing and verifying the operation of error

A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multiword bus eliminating any delay in address incrementing.

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Billerica, MA, United States of America

Robert B Johnson