Motorola Corporation

Robert B Jarrett

Wilson D Pace

James J LoCascio

John M Pigott

Randall C Gray

Byron G Bynum

Robert A Neidorff

Robert M Hess

Robert Bruce Davies

W Eric Main

Edward E Li

Don W Zobel

Robert C Rumbaugh

Howard F Weber

Karl R Heck

A correction circuit (12) for providing an error correction voltage for a voltage reference (11). The voltage reference (11) provides a reference voltage within a predetermined temperature range. The voltage reference prior to correction has a peak magnitude at a temperature T.sub.0 within the predetermined temperature range. A first circuit (13) generates a correction current. Zero current is provided by the first circuit (13) at T.sub.0. A second circuit (14) receives the correction current and provides an output current that is uni-directional or of the same sense above and below T.sub.0. [Means responsive to t] The output current of the second circuit (14) generates a voltage across a resistor (28) that is [combined] added to the reference voltage above and below T.sub.0.

Curvature correction circuit for a voltage reference

A circuit for discharging an inductive load of an H-bridge circuit at a controlled rate has been provided. When a first half of the H-bridge circuit is switched from a conductive state to a non-conductive state, the circuit clamps a first side of the inductive load, while creating a recirculation path to discharge the inductive load at a controlled rate. A similar circuit may be utilized when a second (complementary) half of the H-bridge circuit is switched from a conductive state to a non-conductive state wherein the similar circuit clamps a second side of the inductive load, while creating a recirculation path to discharge the inductive load at a controlled rate.

H-bridge flyback recirculator

A comparator circuit is provided compatible with CMOS logic levels for the input signal and including a substantially zero standby current when the input signal is initially less than the upper trip threshold. The trip threshold follows a bandgap voltage with a zero temperature coefficient, while hysterisis is provided with the upper and lower trip thresholds. An alternate embodiment of the comparator circuit provides a selectable zero temperature coefficient for the trip threshold as a ratio of emitter resistors while maintaining the hysterisis with the upper and lower trip thresholds.

Low standby current comparator having a zero temperature coefficient

A thermally protected power transistor comprising a first chip which includes a power transistor and a second chip which includes protection circuitry. The second chip has a plurality of metallic bumps formed thereon which are coupled to various portions of the protection circuitry, wherein at least one metallic bump serves as a thermal couple. The protection circuitry chip is mounted upside down on the power transistor chip and coupled to the power transistor chip by the metallic bumps. The metallic bumps serve to provide electrical power for the protection circuitry, to couple control signals between the protection circuitry and the power transistor, and to couple thermal information from the power transistor to the protection circuitry.

Thermal protection method for a power device

A comparator circuit with hysteresis does not require any bias current as long as the input signal applied thereto is less than a lower threshold value of the comparator. The comparator includes a current source for providing a plurality of currents when enabled, a Zener diode coupled to the current source for initially enabling the former as the input signal exceeds an upper threshold value, an output circuit which when rendered operative is placed in parallel to the Zener and disables the same while maintaining the current source enabled and providing an output signal from the comparator, and an amplifier responsive to the current source which renders the output circuit operative as the magnitude of current sourced thereto exceeds a predetermined value. A feature of the comparator circuit is that the currents flowing in the output circuit and amplifier have complementary temperature coefficients whereby the composite temperature coefficient of the upper and lower threshold values of the comparator can be adjusted to have a substantially zero temperature coefficient.

Comparator circuit

A regulator is responsive to an input signal proportional to the system supply voltage for adjusting the current flowing in the field windings of an electrical alternator which controls the output power thereof. The primary regulation loop of the regulator generates a pulse train having a duty cycle inversely proportional to the amplitude of the input signal while an oscillator provides a sawtooth signal at a predetermined frequency which controls the response frequency of the regulator. The regulator limits the rate of increase in the duty cycle of pulse train upon detecting a decrease in the system supply voltage by converting the duty cycle of the pulse train to a charging signal for developing a voltage across a capacitor proportional to the duty cycle of the pulse train. The voltage across the capacitor is compared to the sawtooth signal and triggers a latch which disables the output signal of the regulator as the duty cycle lengthens in response to the decrease in the system supply voltage. The voltage across the capacitor is increased each oscillator cycle until the duty cycle reaches the value required to support the output power of the alternator.

Load response control and method

A negative voltage clamp circuit is coupled to an N-epi region within an IC for clamping the voltage applied thereto to a predetermined negative value without utilizing a negative power supply. A current supply provides a first current through a series combination diode and resistor such that a voltage is developed across the resistor. The base of a first transistor receives drive current from the current supply for providing a second current flowing through its collector-emitter conduction path. The first and second currents respectively flow through the collector-emitter conduction paths of second and third transistors which are configured as a cross-coupled pair. The base-emitter junction of the third transistor is responsive to an applied voltage for gating an appropriate magnitude of the second current to the output for limiting the applied voltage to a predetermined value approximately equal to the voltage developed across the resistor.

Negative voltage clamp

A method for limiting short circuit current flow in a Field Effect Transistor (FET) to limit the power dissipated therein includes sensing a rise in the drain-to-source voltage of the transistor and clamping the gate-to-source voltage to a predetermined adjustable value thereby reducing the magnitude of the short circuit current flow to within the safe operating characteristics of the device. A comparator switch circuit is responsive to the drain-to-source voltage of the FET exceeding a reference voltage value for clamping the gate-to-source voltage to a predetermined reduced voltage. A trimmable resistive network is connected between the gate and the source electrode of the transistor for adjusting the gate to source clamped voltage potential to compensate for variations in transistor transconductances from one transistor to the next that they may be used in conjunction with the electronic circuitry.

Method and circuit for providing adjustable control of short circuit

An improved comparator circuit of the type which includes first and second differential PNP transistors operating in conjunction with a current mirror circuit includes an additional dual collector PNP transistor. That is, while the reference voltage is applied to the base of one of the differential transistors, the input voltage to be compared with the reference voltage applied to the emitter of the dual collector's transistor which has a first collector coupled to the base of the other differential transistor. The second collector is coupled to the base of the additional transistor. In this manner, should the input voltage fall below the substrate voltage, the additional transistor will be reverse biased thus preventing the parasitic diode at the base of the second differential transistor from turning on.

Comparator with substrate injection protection

There is disclosed an ignition control circuit of the type which facilitates the storage of energy in an external inductive load during a dwell period and the release of the stored energy from the inductive load through a spark gap at the end of the dwell period. The circuit includes switch means for conducting current through the inductive load during the dwell period, and an integrated circuit for turning the switch means on during the dwell period and off at the end of the dwell period. The integrated circuit includes an output transistor for controlling the switch means, a current source for driving the output transistor, and control means for enabling the current source during the dwell period and disabling the current source at the end of the dwell period.

Ignition control integrated circuit having substrate injection

This relates to a circuit for clamping the voltage across first and second terminals (in this case the gate and source electrodes of a power MOSFET) in response to the receipt of a signal indicating a load fault. An input turnaround transistor receives the signal indicative of the fault and generates a current in response thereto which is applied to the base of a switching transistor. When this current exceeds a predetermined value, the switching transistor turns on which in turn causes a buffer circuit including a PNP transistor to turn on. When the buffer circuit turns on, current is drawn through a zener diode which is coupled to the second terminal. Thus, the clamping circuit between the gate and source terminals equals the voltage drop across the zener diode plus that dropped across the buffer circuit plus the saturation voltage of the switching transistor. Resistors are provided in the buffer circuit to provide for a certain amount of adjustment of the clamping voltage.

Clamp circuit

A short detection circuit and method for operatively controlling current in an electrical load such as an alternator field coil includes a driving device such as a Darlington transistor for driving the electrical load. Detecting means selectively withhold and provide operating current to the driving means when a shorted and not shorted condition of the electrical load is respectively detected at the driven terminal of the driving device.

Short detection circuit and method for an electrical load

This relates to a comparator circuit for monitoring intelligence on a data bus, which circuit consumes no power until activated by a predetermined voltage on the data bus. An input PNP transistor has a base coupled to the data bus. An emitter resistor and a collector resistor may be scaled to achieve a desired switching threshold. A second PNP transistor has a base coupled to the bus and an emitter coupled to the collector of the first PNP transistor such that the second PNP transistor does not turn on until the first PNP transistor saturates. The collector of the second PNP transistor is coupled to the base of an output NPN transistor and supplies drive thereto when the second PNP transistor is on.

A variable temperature coefficient level shifter includes a circuit which generates a voltage V.sub.BE having a negative temperature coefficient and a voltage .DELTA.V.sub.BE having a positive temperature coefficient. A control current is generated by placing a first resistor between V.sub.BE and ground and a second resistor between .DELTA.V.sub.BE and ground. Each of these currents forms a component of the control current which then has some net temperature coefficient. By properly scaling the resistors the control current may have any desired temperature coefficient between 2800 ppm and 3000 ppm. Once the temperature coefficient is set, a third resistor is provided through which the control current flows. The amplitude of the shift is then selected by selecting the value of resistor R.sub.S.

Variable temperature coefficient level shifting circuit and method

An electronic ignition system which is responsive to timing signals generated in timed relationship for providing a substantially constant percent excess dwell time. The timing signals are developed across a sensor coil that is floated between first and second inputs of the system. A capacitor is coupled through a buffer circuit to one of the inputs of the system wherein the timing signal is superimposed onto the voltage developed across the capacitor. A charge and discharge circuit comprising a pair of resistive current sources is utilized to charge and discharge the capacitor during operation. The ratio of the resistive components produces a constant percent excess dwell time that is substantially independent to temperature and process variations.

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Tempe, AZ, United States of America

Robert B Jarrett