International Business Machines Corporation

Robert B Hitchcock

Jeffrey Paul Soreff

Wilm Ernst Donath

Eduardo Kellerman

John P Koons

An apparatus and method for simulating timing performance of designs of digital machines which allows for the avoidance of lumping of correlation of correlation coefficients which may be significant to the slacks which may occur in a particular design. Delays of particular digital elements are derived by random selections from distributions of delay values based on correlations between different observed or otherwise reasonable distributions of relative delays of digital element pairs including pairs of senses of logic value transitions, pairs of technologies and pairs of packaging levels as an accuracy enhancement. Delay distributions are built up of weighted sums of other distributions and may be asymmetrical. Several computational enhancements disclosed include arrangements allowing reductions in paging (e.g. reduction in number of accesses to secondary memory). Other enhancements include application enhancements by providing generality of methodology and accommodation of large model size, further computational enhancement by providing generality of delay propagation algorithms and diagnostic enhancements by providing cycle time/yield data and allowance of re-simulation of failure modes of design performance by retaining seed values corresponding to simulated machines.

Method for evaluating the timing of digital machines with statistical

A printed circuit board for electric circuits is formed of plural layers of electrical conductors and includes through holes and vias arranged in a regular pattern along points of a grid laid out along othorgonal axes of a Cartesian coordinate system. Electrical components such as circuit chips and discrete components are to be mounted to the through holes, while the vias connect electrical conductors of different layers. Conductors of a layer are grouped together as multiple-conductor channels which are routed among the through holes and the vias to make electrical connections among the electrical components. An additional via can be entered in a central portion of a grid cell by rerouting conductors of channels in the cell through arcuate segments, thereby permitting connection between conductors of channels on different layers while preserving the original grid pattern of through holes and vias.

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Wappingers Falls, NY, United States of America

Robert B Hitchcock