Cirrus Logic Inc.

Freescale Semiconductor,inc.

Robert Arthur Jensen

Dimitris Pantelakis

Vikram Shenoy

John L Melanson

Alexander Hoefler

Matthew B Rutledge

Mark S Aurora

Khoi Van Dinh

James S Ledford

Brian E Cook

Alex S Yap

Mail Khoi

A device for reducing the effects of leakage current within electronic devices is disclosed. In one form, a high voltage driver includes a high voltage source coupled to at least one high voltage transistor and a leakage offset module coupled to at least a portion of one of the high voltage transistors. The leakage offset module includes a diode connected MOS device operable to generate an offset voltage and an MOS shunting device coupled in a parallel with the diode connected MOS device. During operation, the diode connected MOS device generates an offset voltage based on a sub-threshold leakage associated with using the high voltage source and the MOS shorting device is operable to short the diode connected MOS device when sub-threshold leakage current is relatively low.

Device for reducing sub-threshold leakage current within a high voltage driver

Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.

Glitch-free memory address decoding circuits and methods and memory subsystems using the same

An integrated circuit has a Built-In Self-Test (BIST) controller ( ) that has a sequencer ( ) that provides test algorithm information for multiple memories ( ). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces ( ) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. This timing information is read prior to performing the test algorithm and is used in performing the test algorithm.

Multiple level built-in self-test controller and method therefor

An apparatus and method for processing a data input signal with a single ended sense amplifier. The single ended sense amplifier includes a transmission gate circuit and a control circuit coupled between a feedback inverter circuit and an output signal that is fed back to the feedback inverter circuit. An inverter circuit is coupled between an enable signal and the transmission gate and control circuits. During pre-charge operation, the input to the feedback inverter circuit is driven to a first state. The feedback inverter correspondingly drives the input signal to a sensing inverter to a state that is complementary to the input to the feedback inverter circuit, thereby assisting the pre-charge mode and substantially reducing time delay due to the input signal contending with the feedback inverter circuit. One advantage of the present invention is that sense amplifiers can be sized for faster sensing than would other-wise be feasible due to the excessive contention during the pre-charge mode.

High speed single ended sense amplifier

A stress test circuit and method for static random access memory (&ldquo;SRAM&rdquo;) cells of an SRAM device are disclosed. The stress test component has a resistance element and a switch component to electrically couple the resistance element between a bit line and complementary bit line of an SRAM cell storing a digital value. Stress test component is activated to electrically couple the resistance element to the bit line and complementary bit line. An electrical path is created causing a voltage on an SRAM circuit path maintaining the digital value to be pulled in one direction by a stress current. The electrical path causes another voltage on another SRAM circuit path maintaining a complementary digital value to be pulled in an opposite direction by the stress current. The SRAM cell is then read to determine whether the digital value has changed state.

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Austin, TX, United States of America

Robert Arthur Jensen