Nvidia Corporation

Emc Corporation

Data General Corporation

Robert Anthony Alfieri

Gary D Hicok

Peter Schuyler Shirley

Paul J Sidenblad

Mark A Parris

John H Edmondson

Marcio T Oliveira

Steven E Molnar

Michael F Harris

Radoslav Danilak

Patrick Rene Marchand

William P Newhall, Jr

Christopher Ryan Wyman

Michael Asbury Woodmansee

Jeffrey S Kimmel

Miles Aram De Forest

Samuel Hammond Duncan

Mark A O'Connell

Paul Thomas McGrath

Rajeshwaran Selvanesan

Duncan Andrew Riach

Brijesh Tripathi

David William Nuechterlein

Robert J Hasslen

James Theodore Compton

John Douglas Tynefield, Jr

William K McGrath

Michael J McLeod

Brian J Thorstad

Khaled S Soufi

Andrew R Huber

Prasad Gharpure

Kelvin Kwok-Cheung Ng

Guy A Simpson

Eric R Vook

Devices, systems, and techniques to incorporate lighting effects into computer-generated graphics. In at least one embodiment, a virtual scene comprising a plurality of lights is rendered by randomly sampling a set of lights from among the plurality of lights prior to rendering a frame of graphics. A subset of the set of lights is selected and used to render pixels within one or more portions of the frame.

Using importance resampling to reduce the memory incoherence of light sampling

One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of importance sampling instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of importance sampling instruction is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of importance sampling instructions on the ray to generate a direction for a secondary ray that is produced when the ray intersects a surface of an object within the 3D environment.

Accelerated processing via a physically based rendering engine

One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of material shading instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of material shading instructions is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of material shading instructions on the ray to generate a color.

One embodiment of a computer-implemented method for decompressing a compressed texture block includes identifying a first texel included in a plurality of texels, wherein the plurality of texels forms at least a portion of a compressed texture block; determining a first location within the compressed texel block that corresponds to the first texel; and extracting the first texel from the first location without decompressing any of the other texels included in the plurality of texels.

One embodiment of a computer-implemented method for compiling a material graph into a set of instructions for execution within an execution unit includes receiving a first material graph having a plurality of nodes, wherein each node included in the plurality of nodes represents a different surface property of a material; parsing the material graph to generate an expression tree that includes one or more expressions for each node included in the plurality of nodes; and generating a set of byte code instructions corresponding to the material graph based on the expression tree, wherein the byte code instructions are executable by a plurality of processing cores included within the execution unit.

One embodiment of a computer-implemented method for processing data within a fixed-function pipeline included in an execution unit includes receiving a first input from a first processing unit, wherein the first input corresponds to a first fixed-function; executing the first fixed-function on the first input to generate a first output, wherein the first fixed-function is executed on the first input prior to executing the first fixed-function on one or more inputs received from a plurality of processing cores that are processing a plurality of rays, and wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment; and transmitting the first output to the first processing unit for further processing.

A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.

Sequential access memory with master-slave latch pairs and method of operating

A system, method, and computer program product are provided for altering a line of code. In use, a line of code is identified, where the line of code is written utilizing both a programming language and one or more syntax extensions to the programming language. Additionally, the line of code is altered so that the altered line of code is written using only the programming language. Further, the altered line of code is returned.

System, method, and computer program product for altering a line of code

A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree.

Power conservation using gray-coded address sequencing

A debugger graphical user interface (GUI) system, method, and computer program product are provided. In use, a list of constructs is displayed a first portion of the GUI of the debugger. Further, waveforms corresponding to the constructs or source code corresponding to the constructs is displayed in a second portion of the GUI of the debugger.

Debugger graphical user interface system, method, and computer program product

Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128&#xd7;1 FIFO even though the FIFO is implemented using a 16&#xd7;8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded.

Folded FIFO memory generator

A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based common representation of a hardware design stored in a hardware model database. Logic code is generated for each hardware module node of the graph-based common representation of the hardware design. Additionally, flow control code is generated for each hardware module node of the graph-based common representation of the hardware design. A logic code model of the hardware design that includes the generated logic code and the generated flow control code is stored.

System, method, and computer program product for translating a common hardware database into a logic code model

One embodiment sets forth a technique for deterministic synchronization of signals that are transmitted between different clock domains. The relative phase difference between a source clock domain and a destination clock domain is characterized and the source clock and/or the destination clock are delayed as needed to generate phase-shifted versions of the source and destination clocks for use during a deterministic operating mode. The phase-shifted versions of the source and destination clocks are non-overlapping, meaning that the rising edge of the destination clock does not occur when the source clock is asserted. The non-overlapping source and destination clocks are used by a deterministic synchronization unit to ensure that signals being transmitting from the source clock domain to the destination clock domain are not sampled within a metastability window.

Growing community of inventors

Chapel Hill, NC, United States of America

Robert Anthony Alfieri