International Business Machines Corporation

Rockwell Collins, Inc.

Mayo Foundation for Medical Education and Research

Robert Andrew Kertis

Raymond Alan Richetta

Timothy Joseph Schmerbeck

Rick Allen Philpott

David Peter Swart

Donald Joseph Schulte

Christian J Goetschel

James Stuart Dunn

Nicholas Theodore Schmidt

Eric D Johnson

Kenneth Knetch Kieft, Iii

Robert A Greene

Albert Edson Lanpher

Michael Dean Hulvey

Richard Leo Galbraith

Jonathan Darrel Coker

Russell David Wyse

Michael L Hageman

Klaas Berend Klaassen

David W Cripe

Peter John Windler

Joe Martin Poss

Bryan S McCoy

Jacobus Cornelis Leonardus Van Peppen

Jaydip Bhaumik

Mark Andrew Berquist

A system and method for operating a system including at least one active electronically scanned array (AESA) element incorporates drain voltage amplifier control (DRAVAC) to maintain the power amplifiers of the AESA elements at a constant gain compression level. A processor of the AESA system may dynamically program, monitor, or adjust each individual array element or component thereof. As the RF output power of the power amplifiers varies, constant gain compression is achieved by dynamically adjusting the RF input power and drain voltage to the power amplifiers. An AESA element may incorporate built-in self-test circuitry for detecting faults in the power supply to the power amplifiers as well as calibrating and calculating RF output power for a given input power by controlling the bias of a pass device serving as the amplifier current source.

Active electronically scanned array with power amplifier drain bias tapering for optimal power added efficiency

A chirp waveform generator for producing a chirp waveform &#x192;(t)=sin (tmodulus m) where modulus m is represented by n submoduli and/or factored submoduli m-m. Sequence generators generate digital sequence values representative of sequences of quadratic residues for each submoduli and/or factored submoduli m-m. Sine and cosine digital-to-analog converters (DACs) connected to the sequence generators receive the digital sequence values for each submoduli and/or factored submoduli m-mand produce sequences of corresponding analog sine and cosine signals. An analog processor including adders and multipliers connected to the DACs combines the sine and cosine signals to produce the chirp waveform. The argument (tmodulus m) is an implemented phase argument that approximates a desired phase argument (&#x3c0;rt). Programmable inputs on the sequence generators enable control over waveform parameters including starting phase, ramp rate and frequency.

Digital chirp waveform generator and method

A circuit is disclosed which adjusts the phase of a signal within an LC sinusoidal or a ring or other capacitive oscillator. The circuit uses FETs as capacitors. The gates of the FETs are connected to the capacitive node of the oscillator. The variable voltage source changes the state of the FET from depleted to inverted mode or from inverted to depleted mode which in turn dramatically changes the capacitance of the FET. The change of state exists for only a few clock cycles, typically less than five cycles, so that only the capacitance within the oscillator is instantaneously affected which changes adds as incremental/decremental frequency to adjust only the phase of the oscillation frequency. In this fashion, the average oscillation frequency not affected.

Phase shift control for voltage controlled oscillator

A circuit arrangement for correcting magneto-resistive head asymmetry includes a shift circuit which receives a read signal from a magneto-resistive head, and a polarity signal indicative of the polarity of any asymmetry of the read signal. Depending on the polarity of the asymmetry, the shift circuit either adds or subtracts a shift voltage to the read signal to produce a shifted read signal. The shift circuit outputs the read signal, the shifted read signal, and the shift voltage. First, second and third gain circuits are provided, which receive the read signal, the shifted read signal, and the shift voltage, respectively, and which each receive a respective control signal. The first, second and third gain circuits provide respective outputs amplified proportionally based on the respective control signals. Control circuitry provides the polarity signal to the shift circuit and the respective control signals to the first, second and third gain circuits, based on an amount of correction required. A common-mode-feedback circuit adjusts for changes in the common-mode caused by the waveform shaping.

Magneto-resistive asymmetry correction circuit

A method and circuits are provided for high speed powerup of an analog reference source, such as used in a direct access storage device (DASD). The high speed powerup circuits for the analog reference source include a biasing current source. Biasing circuitry is provided for establishing a first bias reference voltage level. An enable input is provided for disabling and for enabling powerup of the analog reference source. A transistor switch is coupled between the bias reference voltage level and the analog reference source. The transistor switch is operatively controlled by the enable input for driving the analog reference source and enabling fast powerup of the analog reference source.

Method and circuits for high speed powerup of analog reference source for a direct access storage device (DASD)

An interleaved finite impulse response (FIR) filter apparatus is provided for data detection in a direct access storage device. The FIR filter includes a plurality of sample and hold circuits. Each sample and hold circuit samples an input signal sequentially at a clock rate. At least one set of multiple multipliers is coupled to the plurality of sample and hold circuits. Each multiplier multiplies a sample by a predefined value and provides a multiplier product at the clock rate. At least a pair of summing functions are coupled to the set of multipliers. Each summing function adds a predetermined combination of respective multiplier products and provides at least a pair of interleave outputs. Each of the interleave outputs is provided at less than the clock rate.

Interleaved finite impulse response (FIR) filter functions for servo and data detection in a direct access storage device (DASD)

A method for detecting servo data and an interleaved dibit detection apparatus are provided for servo data detection in a direct access storage device. The interleaved dibit detection apparatus includes a new dibit threshold detector for detecting a predefined threshold level of a new interleave servo signal and providing a new detected dibit output. An old dibit threshold detector detects the predefined threshold level of an old interleave servo signal and provides an old detected dibit output. A combining function coupled to the new dibit threshold detector and the old dibit threshold detector provides a combined detected dibit output.

Interleaved dibit detection for direct access storage device (DASD)

A signal multiplier is provided for use in multiplying an analog differential signal. The analog differential signal is defined by a first analog attribute and a second analog attribute. Preferably, a means is provided for generating a first current which corresponds to the first analog attribute. Additionally, a means is provided for generating a second current which corresponds to the second analog attribute. A first amplifier member is provided for receiving the first current as an input and providing as an output a multiple of the first current. Additionally, a second amplifier is provided for receiving the second current as an input and producing as an output a multiple of the second current. A tuneable multiplier member is provided for determining the multiple over a predetermined range of multiples. A means for maintaining a substantially linear response of the signal multiplier is also provided. The means for maintaining the substantially linear response of the multiplier provides at least approximately two orders of magnitude in multiplication. The means for maintaining a substantially linear response of the signal multiplier includes a means for utilizing base current cancellation in order to minimize the influence of particular base currents from particular analog circuit components which would otherwise limit the linear response of the analog signal multiplier of the present invention.

Method and apparatus for providing analog differential signal

A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders. A positive phase and negative phase emitter follower transistor pair is connected to the pair of series connected resistor ladders. The positive phase and negative phase emitter follower transistor has a collector connected to a supply voltage and has an emitter coupled to a respective one of the pair of series connected resistor ladders. A respective positive phase and negative phase AC current source drives the base of the respective positive phase and negative phase emitter follower transistor. A reference DC current source is coupled to the base of the positive phase and negative phase emitter follower transistors for determining a range of the ADC. A current source transistor pair biases the emitter follower transistor pair. A first transistor of the current source transistor pair supplies current to the positive phase emitter follower transistor and a second transistor of the current source transistor pair supplies current to the negative phase emitter follower transistor. The first transistor has a control node capacitively coupled to the emitter of the negative phase emitter follower transistor and the second transistor having a control node capacitively coupled to the emitter of the positive phase emitter follower transistor.

Current boost for differential flash analog to digital converter driver

High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

Method of forming high performance bipolar devices with improved wiring

High performance bipolar devices with plurality of base contact regions

A method and apparatus are provided for translating small voltage continuous signals into large full supply signals to generate a clock signal. At least one oscillator input signal is applied to a first amplifier stage for generating an amplified voltage output signal. A first inverter is coupled to the first amplifier stage. A second inverter is coupled to the first inverter. An AC coupling capacitor couples the amplified voltage output signal to the first inverter input, and a feedback resistor is connected between the output and input of the first inverter.

Method and apparatus for generating a clock signal from a continuous

An integrated biquadratic, continuous-time filter section includes a plurality of operational transconductance amplifiers (OTAs). Simutaneously changing a transconductance (GM) of each of the OTAs is provided by adjusting a differential voltage applied to a plurality of differential transistor pairs of each OTA. Each of the OTAs include a plurality of current sources and a common mode feedback circuit for controlling a common mode output voltage level. Changing the transconductance of the OTA is independent of the common mode voltage level control.

Operational transconductance amplifier with independent transconductance

A method and apparatus are provided for adaptive chip trim adjustment for an integrated circuit. A plurality of switching devices have an unswitched state and a switched state. The unswitched state corresponds to one binary value, and the switched state corresponds to another binary value. A first trim word is provided by sensing the switching devices. The switching devices are temporarily bypassed, and an override bit pattern is supplied to simulate any desired pattern of the switching device states. The override bit pattern is used for simulating a switched or unswitched state for each of the plurality of switching devices.

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Rochester, MN, United States of America

Robert Andrew Kertis