International Business Machines Corporation

Robert Allan Faust

Mike Conrad Duron

Michael Anton Barenys

Joel Gerald Goodwin

Forrest Clifton Gray

George Henry Ahrens, Jr

John Daniel Upton

Joel Gerard Goodwin

Kurt Paul Szabo

William Eldred Beebe

Ajay Kumar Mahajan

Glenn Rueban Miles

Craig Henry Shempert

Charles Andrew McLaughlin

Stephan Otis Broyles

Gary Lee Ruzek

Kevin Gene Kehne

John C Kennel

Sayileela Nulu

Christopher Lawrence Canestaro

A JTAG bus cross point switching device that is commanded by the same bus which it configures. In a preferred embodiment a JTAG chain includes a cross point switching device that is capable of adding, omitting, or rearranging devices on a JTAG bus. The switching device itself is controlled by commands on the JTAG bus which it configures.

JTAGchain bus switching and configuring device

A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.

Method and apparatus for generating multiple analog signals using a single microcontroller output pin

A method, apparatus, and computer program product are disclosed for monitoring and controlling a device using only one input/output (I/O) communication pin of the device. The pin is configured to be used to both transmit and receive data. Logical ones are generated using pulses that are a first length and logical zeros are generated using pulses that are a second length. The device is communicated with utilizing the generated logical ones and generated logical zeros by transmitting the logical ones and zeros to the device, and receiving the logical ones and zeros from the device utilizing the single I/O pin.

Apparatus, method, and computer program product for monitoring and controlling a microcomputer using a single existing pin

Commanding a JTAG bus cross point switching device by the same bus which it configures. Adding, omitting, or rearranging devices on a JTAG bus with a cross point switching device that is included in a JTAG chain. Controlling the switching device with commands on the JTAG bus which it configures.

An IC device is disclosed that includes a main IC section, bus switches, switch logic, and address logic as part of the IC device. The IC device is coupled to an IC bus for communicating with other IC devices and an IC bus controller that is also on the IC bus. The switch logic controls a current position of the switches. The IC device is coupled to the IC bus utilizing the switches. The switches control whether the main IC section, the address logic, the switch logic, or a combination of the main IC section, address logic, and switch logic is currently coupled to IC bus. The switches also can be used, if desired to remove from the buss all devices that are downstream from a given device containing switches. The address logic is used to receive and store the address of the IC device. The IC device will respond to the address that is stored in its address logic.

[object Object]

A method of accessing an embedded microcontroller, by programmably selecting pins of the microcontroller for use as test lines, receiving a scan command at an input test line pin, emulating a virtual scan path through a logical block of the microcontroller, and transmitting scan results to an output test line pin. The microcontroller can provide such emulation of scan testing in compliance with the JTAG standard for a test access port and boundary-scan architecture. The test line pins are interconnected with a test bus structure to form a scan ring with other components of a data processing system, such as a microprocessor. The emulation can be used to change a functional mode of the microcontroller, or gather diagnostic information after a system error. The microcontroller assigns a high-priority internal interrupt routine to service test line pin activity. The virtual scan path need not include all internal microcontroller resources, and the scan path can be programmably varied by the application designer.

Method and apparatus for diagnosis and behavior modification of an embedded microcontroller

A method, apparatus, and computer implemented instructions for saving data in a logically partitioned data processing system. An error is detected in the logically partitioned data processing system. Data needed for error analysis of the error is saved in a power independent memory associated with a service processor.

Method and apparatus for saving data used in error analysis

An apparatus and method for error logging on a memory module, such as a DIMM, are provided. If an error occurs in a memory module, the operating system of the computing device stores a log of the error in a storage device mounted to the memory module. The log may identify the type and quantity of errors caused by the faulty memory module and may also include defective bit identification information. The defective bit identification information may be used to identify individual memory elements on the memory module that are defective. If the errors exceed a given quality or quantity level, the operating system may store an indicator in the storage device on the memory module that the memory module is defective and take that memory module off-line to prevent problems from occurring with the programs that are running on the computing system.

Apparatus and method for error logging on a memory module

A method system, and computer program product for determining the source of a fault within a bus, such as, for example, an inter integrated circuit (I2C) bus is provided. In one embodiment, a bus driver monitors the bus for faults. If a fault occurs on the bus, the bus driver resets each switch on the bus and then turns on the first switch connected to the bus driver. If the fault is encountered after turning on the first switch, then it is determined that the fault was caused by either the first switch, a device connected to the bus as a result of turning on the first switch, or one of the bus connectors just switched on as a result of turning on the first switch. If the fault is not encountered, the next switch is turned on and the process is repeated until the fault is encountered. The fault when encountered will be caused by either the most recently turned on switch or a device or bus connectors switched in by the turning on of the last switch. Thus, the fault can be isolated to a few devices, switches, or bus connections rather than the large number of potential devices, switches, or bus connections that could have potentially caused the fault.

Method for isolating an I2C bus fault using self bus switching device

A method, apparatus and program for dynamically allocating addresses to computer devices connected to Inter Integrated Circuit (I C) buses are provided. Upon resetting a I C bus, the invention uses a bus driver to turn on the first bus switch on the bus. The invention then accesses the first device downstream of the switch and allocates a new value to the device's address. The invention proceeds to turn on the next switch downstream. A new address is then allocated to the device downstream from the second switch. This process continues until all of the devices connected to the bus have unique addresses.

Dynamically allocating I2C addresses using self bus switching device

A bus switch module for use in a bus such as an I2C bus is provided. In one embodiment, the switch module includes a control unit and a switch. The control unit includes an input for receiving instructions from a bus driver as to whether to close or open the switch. The switch includes a first and a second data connection which connect the switch to a first and a second segment of the bus and includes a control input for receiving commands from the control unit. The control unit opens and closes the switch in response to instructions received from the bus driver and signals received in the first data connection are passed to the second data connection only when the switch is closed in response to a command from the control unit.

I2C bus switching devices interspersed between I2C devices

A debug card suitable for use with a data processing system is disclosed. The card includes a microcontroller, a storage device connected to the microcontroller; and, connected to the microcontroller, means for tapping into a communication bus of the data processing system where the bus communicates information between a processor of the data processing system and a display panel. The microcontroller is configured to record the information received by the display panel from the processor in the storage device when the debug card is connected to the communication bus. In one embodiment, the communication bus and the microcontroller are I C compliant. In this embodiment, the debug card may have its own I C address thereby enabling the debug card to communicate with the processor. The debug card may further include a serial port connected to the microcontroller. The serial port enables downloading the information stored in the storage device to an external computer. In addition, a user of the external computer may send commands to the data processing system through the serial port to customize the debug session. The debug card may further include a non-volatile storage device containing software enabling the microcontroller to communicate information to the processor. The means for tapping into the communication bus may include a tee connector having a debug port and a communication bus port. In this embodiment, a communication bus ribbon cable is connected to the communication bus port and a debug cable is connected to the debug port. At least a portion of the signals of the communication bus are routed to the debug card via the tee connector and the debug cable. The debug card may include a battery connected to the storage device and suitable for retaining the information in the storage device when external power to the debug card is disconnected.

External debug card sharing a communication bus

A method and system comprising at least one service processor that is connected to memory and a host system. Additionally, the host system includes at least one host input resource device, such as, for example, a floppy disk, and an interface connecting the host input resource device to the service processor. The interface provides a means for the host input resource device to update, restore, or initialize host system parts or images. In one embodiment, this invention disconnects the host input resource device from main system power and connects it to auxiliary standby power. Thus, the host input resource device makes possible a less costly, less burdensome update of any piece of a data processing system.

Growing community of inventors

Austin, TX, United States of America

Robert Allan Faust