Stmicroelectronics Gmbh

Robert Alan Wadsworth

David C McClure

Sooping Saw

Richard Ferrant

An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode. More specifically, the second circuit operates to drive the alarm output pad with the tamper alarm signal when the integrated circuit is not in test mode and drive the test mode output pad with the tamper alarm signal when the integrated circuit is in test mode (with the alarm output pad driven to a known state).

Test mode circuitry for a programmable tamper detection circuit

Programmability of the data background patterns used to test random-access-memories (RAMs) is accomplished by adding to the memory input/output (I/O) buffers of RAM memory, for each data bit of a data background pattern to be programmed, a programming mechanism and a selection mechanism. The programming mechanism is capable of programming a data bit of the data background pattern in accordance with a programming information signal provided to the RAM. The selection mechanism provides either the programmed data bit or a normal, application data bit to an input/output buffer of the RAM in accordance with whether the RAM is in a test mode or a normal operating mode, as indicated by a test control signal provided to the RAM.

Growing community of inventors

Coppell, TX, United States of America

Robert Alan Wadsworth