Andigilog, Inc.

Other

Standard Microsystems Corporation

Dolpan Audio, LLC

Robert Alan Brannen

Jade H Alberkrack

Thomas Peter Bushey

David Cave

A digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the timing delay circuits are substantially eliminated.

Digital delay circuit

A method of operating a direct current motor fan assembly is provided in which a motor controller operates to apply full power to kick-start a motor to overcome static forces. As soon as a sensor determines that the motor has begun to rotate, the motor controller changes the motor drive level from full power to a predetermined lower level to maintain a desired rotational speed.

DC motor variable kick-start

A motor controller for a direct current motor includes a first node receiving first PWM signals having a duty cycle indicative of a desired rotational speed of said motor and an input node receiving second digital signals, the frequency of said second signals indicative of the rotational speed of said motor. A frequency-to-PWM circuit is coupled to the input node to provide second PWM signals having a duty cycle corresponding to the rotational speed of the motor. A duty cycle comparator has a first input coupled to the first node and a second input coupled to the second node to generate a control signal for controlling the rotational speed of the motor.

Fan controller with duty cycle comparator

A method and apparatus is provided for processing signals from a Hall-effect device arrangement coupled to a monolithic brushless DC motor where the motor is driven by a PWM circuit providing PWM drive signals.

Noise suppression for hall sensor arrangements

A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals.

Duty cycle comparator

In accordance with the principles of the invention, an integrated circuit comprises a substrate having a first FET formed on the substrate. The first FET has a first terminal coupleable to a load, a second terminal and a control terminal. The second terminal is connected to the substrate. The substrate comprises a parasitic body diode coupled between the first terminal and the substrate. The body diode is disposed such that it becomes conductive when a reverse voltage across the FET first terminal and the substrate is at least a first diode forward voltage. A voltage detector is formed on the substrate. The voltage detector has a first input coupled to the FET first terminal, a second input coupled to the substrate, and an output coupled to the FET control terminal. The voltage detector is responsive to a reverse voltage level at the FET first terminal that is less than the first diode forward voltage to turn the FET on for the duration of a reverse voltage having at least said reverse voltage level. The parasitic body diode is thereby prevented from injecting current into the substrate.

Synchronous substrate injection clamp

A method and apparatus is provided for processing signals from a Hall effect device arrangement coupled to a monolithic brushless DC motor where the motor is driven by a PWM circuit providing PWM drive signals.

Noise suppresion suppression for hall sensor arrangements

A PWM controller for a direct current brushless motor comprising first and second windings includes a motor drive circuit receiving pulse width modulation control signals to drive the first and the second windings; and a control circuit having inputs coupled to the first and second windings to control a pulse width modulation control circuit such that pulse width modulated control signals are provided to the motor drive circuit only when the voltage across the first and second windings are at a predetermined level.

Controller arrangement with adaptive non-overlapping commutation

A method and apparatus of interfacing a Hall sensor to a commutation circuit comprises receiving output signals from the Hall sensor; detecting when the Hall sensor output signals are within a predetermined range; generating commutation output signals when the Hall sensor output signals are in a predetermined state for a predetermined period of time; and locking out a change in the commutation output signals for a second predetermined period of time.

Motor controller with enhanced noise immunity unbuffered hall sensors

A control circuit is described in which a single input terminal receives digital control signals and analog control signals. In accordance with the principles of the invention, the control circuit includes an automatic power down circuit to place the control circuit into a low power draw or 'sleep' mode whenever predetermined conditions are present. The automatic power down circuit monitors the single input terminal and when no demand for motor operation occurs for a predetermined period of time, the automatic power down circuit operates to place the control circuit into the low power draw mode.

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Chandler, AZ, United States of America

Robert Alan Brannen