Lucent Technologies Inc.

Agere Systems Inc.

Agere Systems Guardian Corp.

Robert Alan Ashton

Daniel Joseph Vitkavage

Steven Alan Lytle

Mary Drummond Roby

Yehuda Smooha

Samir Chaudhry

Morgan J Thoma

Alan R Massengale

Jinghui Ning

Glenn C Abeln

The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.

Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof

A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable of carrying considerable current at a reduced voltage once it snaps back into bipolar operation mode after its trigger point is achieved. The snapback device includes the advantage of a low breakdown voltage which enables the snapback device to snap back into bipolar mode before damage is done to active circuit components due to their breakdown voltages being exceeded. The snapback device includes n active areas formed within a p-well substrate region and each active area includes a polysilicon film overlapping the active area but insulated therefrom by a dielectric film. Each n active area and polysilicon film are coupled by a conductive film and the components combine to form one electric node. One electric node of the snapback device is coupled to I/O terminals of the device and the other is coupled to ground or a power supply.

Polysilicon bounded snapback device

A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.

Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies

A method for making an integrated circuit includes the steps of forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween, forming a first mask, and using the first mask for performing at least one implant in the active regions for defining high voltage active regions for the high voltage transistors. The method further includes the steps of removing the first mask and forming a second mask, and using the second mask for performing only one implant for converting at least one high voltage active region into a low voltage active region for a low voltage transistor. All of the implants needed to define the high voltage transistors are first performed throughout the active regions using the first mask. A separate single implant is then performed using the second mask to convert at least one of the high voltage active regions to a low voltage active region. A gate dielectric layer is formed on the high and low voltage active regions for corresponding high and low voltage transistors, and gates are formed on the gate dielectric layers.

Method for making an integrated circuit including high and low voltage transistors

The present invention provides a van der Pauw semiconductor test structure for and a method of testing a resistivity of a doped area formed within a substrate of a semiconductor wafer which may be under a diffusion area or a gate structure. The test structure can include field oxide regions formed on a surface of the substrate and a base doped substrate formed within the substrate. Further, the test structure includes a first primary tub and secondary tubs that are formed within the base doped substrate, each of the secondary tubs having a first diffusion region formed adjacent to an inner isolation structure and a second diffusion region formed adjacent to an outer isolation structure. A second primary tub is located adjacent the first primary tub and a dielectric layer is formed over the substrate having contacts formed within the dielectric layer and between the isolation structures. Further still, the test structure may include a gate structure as part of the semiconductor test structure, with the gate structure having openings formed therein through which the contacts extend to the first diffusion regions and the second diffusion regions.

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Orlando, FL, United States of America

Robert Alan Ashton