Logicvision, Inc.

Synopsys, Inc.

Magma Design Automation, Inc.

Robert Abbott

Benoit Nadeau-Dostie

R Dean Adams

Dirk Pfaff

Ralph Mason

Dwayne M Burek

Xiaoliang Bai

Christopher Falkingham

The present disclosure describes circuits (e.g., clock synthesizers) and methods for producing alternating signals. A clock synthesizer includes an oscillator, a voltage control circuit, and a frequency control circuit. The oscillator produces an output signal with a frequency. The voltage control circuit produces a control voltage for the oscillator based on the frequency of the output signal. The frequency control circuit produces a control signal for the oscillator based on (i) an input voltage to the frequency control circuit and (ii) the control voltage. The control signal causes the oscillator to adjust the frequency of the output signal such that the voltage control circuit adjusts the control voltage to be closer to the input voltage.

Clock synthesizer with dual control

A memory logic built-in self-test ('BIST') includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.

Asynchronous control of memory self test

A method and circuit for repairing a memory array having one or more memory segments each having one spare column and a predetermined number of spare rows common to all segments, the method comprises, while testing the memory array for failures, generating an equal number of unique segment repair solutions for each segment with each segment repair solution including one defective column address, if any, and a number of defective row addresses, if any, corresponding to the predetermined number of spare rows; and, after completing testing, analyzing all segment repair solution combinations consisting of one segment repair solution selected from each segment; and identifying the best segment repair solution combination of combinations having a number of different defective row addresses which is less than or equal to the predetermined number of spare rows.

Memory repair analysis method and circuit

A memory test controller comprises a test instruction register array for storing a plurality of test instructions, each register having instruction fields for storing instruction data specifying operations to be performed on the memory array, a repeat module for repeating a group of one or more of the test instructions with modified data, the repeat module including storage means for storing instruction field modification data; and each register of the test instruction register array including an instruction field for enabling or disabling the repeat module.

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Ottawa, Canada

Robert Abbott